Inventor
MANDAVA SREENIVAS
US14 patents
Patents
14 patentsUS9449671B2Sep 20, 2016
Techniques for probabilistic dynamic random access memory row repair
INTEL CORP20 citations92
US9269436B2Feb 23, 2016
Techniques for determining victim row addresses in a volatile memory
INTEL CORP7 citations81
US12235720B2Feb 25, 2025
Adaptive error correction to improve system memory reliability, availability, and serviceability (RAS)
INTEL CORP3 citations73
US10102886B2Oct 16, 2018
Techniques for probabilistic dynamic random access memory row repair
INTEL CORP4 citations73
US9824754B2Nov 21, 2017
Techniques for determining victim row addresses in a volatile memory
INTEL CORP3 citations70
US12417042B2Sep 16, 2025
Detection of data corruption in memory address decode circuitry
INTEL CORP0 citations62
US12347507B2Jul 1, 2025
Method and apparatus for memory chip row hammer threat backpressure signal and host side response
INTEL CORP0 citations62
US12321622B2Jun 3, 2025
Deferred ECC (error checking and correction) memory initialization by memory scrub hardware
INTEL CORP0 citations51
US12099388B2Sep 24, 2024
Temperature-based runtime variability in victim address selection for probabilistic schemes for row hammer
INTEL CORP0 citations51
US10552643B2Feb 4, 2020
Fast boot up memory controller
INTEL CORP0 citations51
US10162761B2Dec 25, 2018
Apparatus and method for system physical address to memory module address translation
INTEL CORP1 citations51
US10042562B2Aug 7, 2018
Apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device
INTEL CORP0 citations51
US9747041B2Aug 29, 2017
Apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device
INTEL CORP0 citations51
US12541460B2Feb 3, 2026
Memory transaction queue bypass based on configurable address and bandwidth conditions
INTEL CORP0 citations50