Inventor

CRAWFORD JOHN H

US37 patents

⚠️ This page may combine multiple inventors who share the name “CRAWFORD JOHN H”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CRAWFORD JOHN H

INTEL CORP

Mapping a physical address differently to different memory devices in a group

Memory management for microprocessor system

Emulation of an instruction set on an instruction set architecture transition

Method of transferring burst data in a microprocessor

Virtual memory management method and apparatus utilizing separate and independent segmentation and paging mechanism

Controller for two-way set associative cache

Method of transferring burst data in a microprocessor

Techniques for probabilistic dynamic random access memory row repair

Transaction based shared data operations in a multiprocessor environment

Apparatus and method for protecting critical resources against soft errors in high performance microprocessors

Computer system and method for executing interrupt instructions in operating modes

Apparatus and method for swapping the byte order of a data item to effectuate memory format conversion

System using both a supervisor level control bit and a user level control bit to enable/disable memory reference alignment checking

Content addressable memory for microprocessor system

Method and apparatus for run-ahead victim selection to reduce undesirable replacement behavior in inclusive caches

Virtual memory mapping using region-based page tables

Techniques for determining victim row addresses in a volatile memory

Synchronizing multiple threads efficiently

Techniques for probabilistic dynamic random access memory row repair

Refresh parameter-dependent memory refresh management

Techniques for determining victim row addresses in a volatile memory

Synchronizing multiple threads efficiently

Computer system and method for executing interrupt instructions in two operating modes

Memory refresh management

Method and apparatus for protecting TLB&#39;s VPN from soft errors

Periodic activity alignment

Synchronizing multiple threads efficiently

Tracking health of integrated circuit structures

Apparatus and method for protecting critical resources against soft errors in high performance microprocessor

KOTTAPALLI SAILESH

Synchronizing multiple threads efficiently

Transaction based shared data operations in a multiprocessor environment

Transaction based shared data operations in a multiprocessor environment

BODAS DEVADATTA V

Managing power consumption and performance of computing systems

Managing the operation of a computing device by determining performance-power states

SONG JUSTIN J

Mechanisms to avoid inefficient core hopping and provide hardware assisted low-power state selection

LEADING PLYWOOD CORP

Wood burner

KUMAR ANIL K

PCIE device power state control

Method and apparatus for protecting TLB's VPN from soft errors