Inventor
TAN MERVYN Y
US9 patents
Patents
9 patentsUS7503020B2Mar 10, 2009
IC layout optimization to improve yield
IBM110 citations97
US7240306B2Jul 3, 2007
Integrated circuit layout critical area determination using Voronoi diagrams and shape biasing
IBM8 citations71
US7818694B2Oct 19, 2010
IC layout optimization to improve yield
IBM2 citations62
US7685553B2Mar 23, 2010
System and method for global circuit routing incorporating estimation of critical area estimate metrics
IBM2 citations62
US7310788B2Dec 18, 2007
Sample probability of fault function determination using critical defect size map
IBM4 citations62
US7302653B2Nov 27, 2007
Probability of fault function determination using critical defect size map
IBM6 citations62
US7634745B2Dec 15, 2009
Method for computing the critical area of compound fault mechanisms
IBM3 citations60
US7661080B2Feb 9, 2010
Method and apparatus for net-aware critical area extraction
IBM4 citations56
US7752589B2Jul 6, 2010
Method, apparatus, and computer program product for displaying and modifying the critical area of an integrated circuit design
IBM0 citations51