Inventor

KWAN MING SANG

US30 patents

⚠️ This page may combine multiple inventors who share the name “KWAN MING SANG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KWAN MING SANG

SPANSION LLC

Ramp gate erase for dual bit flash memory

Variable salicide block for resistance equalization in an array

Multi-phase wordline erasing for flash memory

Cycling improvement using higher erase bias

Using implanted poly-1 to improve charging protection in dual-poly process

Thin oxide dummy tiling as charge protection

Using thick spacer for bitline implant then remove

Deep bitline implant to avoid program disturb

ADVANCED MICRO DEVICES INC

Adjustable threshold voltage conversion circuit

Flash memory cell programming method and system

Memory circuit arrangement for programming a memory cell

Method for making semiconductor circuit including non-ESD transistors with reduced degradation due to an impurity implant

Reduction of field oxide step height during semiconductor fabrication

Method and semiconductor circuit for maintaining integrity of field threshold voltage requirements

CYPRESS SEMICONDUCTOR CORP

NAND memory cell string having a stacked select gate structure and process for for forming same

NAND memory cell string having a stacked select gate structure and process for for forming same

NAND memory cell string having a stacked select gate structure and process for for forming same

NAND memory cell string having a stacked select gate structure and process for forming same

NAND memory cell string having a stacked select gate structure and process for for forming same

HYUNDAI ELECTRONICS AMERICA

Method of operating flash memory

Triple well flash memory fabrication process

Method of operating flash memory

Source side programming

SPANSION L L C

Methods and systems for reducing erase times in flash memory devices

Flash memory device having increased over-erase correction efficiency and robustness against device variations

ADESTO TECH CORP

Resistive switching memory device architecture for reduced cell damage during processing

Resistive switching memory having a resistor, diode, and switch memory cell

ADESTO TECHNOLOGIES CORP

Capacitor arrangements using a resistive switching memory cell structure

Programmable impedance memory device and related methods

SINHA SHANKAR

Barrier region underlying source/drain regions for dual-bit memory devices