Inventor

GOPINATH VENKATESH P

US43 patents

⚠️ This page may combine multiple inventors who share the name “GOPINATH VENKATESH P”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GOPINATH VENKATESH P

GLOBALFOUNDRIES US INC

Partitioned memory architecture and method for repeatedly using the architecture for multiple in-memory processing layers

Calibration methods and structures for partitioned memory architecture with single resistor or dual resistor memory elements

Partitioned memory architecture with single resistor or dual resistor memory elements for in-memory pipeline processing

Partitioned memory architecture with dual resistor memory elements for in-memory serial processing

Resistive memory elements accessed by bipolar junction transistors

Transistor arrays with controllable gate voltage

Partitioned memory architecture with single resistor memory elements for in-memory serial processing

Threshold voltage-programmable field effect transistor-based memory cells and look-up table implemented using the memory cells

Non-volatile static random access memory bit cells with ferroelectric field-effect transistors

Structure including a cross-bar router and method

Threshold voltage-programmable field effect transistor-based memory cells and look-up table implemented using the memory cells

Capacitor integrated with memory element of memory cell

Non-volatile current mirror circuit with programmable transistor

Programmable delay circuit including threshold-voltage programmable field effect transistor

Non-volatile memory device with reference voltage circuit including column(s) of reference bit cells adjacent columns of memory bit cells within a memory cell array

LSI LOGIC CORP

Fabrication of trenches with multiple depths on the same substrate

Shallow trench isolation structure for laser thermal processing

Process for improving mechanical strength of layers of low k dielectric material

Voltage level shifter

Method of manufacturing a shallow trench isolation structure with low trench parasitic capacitance

Method of forming an antifuse on a semiconductor substrate using wet oxidation of a nitrided substrate

Fabrication of trenches with multiple depths on the same substrate

Etch resistant shallow trench isolation in a semiconductor wafer

Method of reducing the effect of implantation damage to shallow trench isolation regions during the formation of variable thickness gate layers

Method characterizing materials for a trench isolation structure having low trench parasitic capacitance

ADESTO TECHNOLOGIES CORP

Pre-conditioning circuits and methods for programmable impedance elements in memory devices

Reference circuits and methods for resistive memories

Capacitor arrangements using a resistive switching memory cell structure

Safeguarding data through an SMT process

Static random access memories with programmable impedance elements and methods and devices including the same

Solid electrolyte based memory devices and methods having adaptable read threshold levels

Memory device having programmable impedance elements with a common conductor formed below bit lines

Memory cells with vertically integrated tunnel access device and programmable impedance element

Programmable impedance memory device and related methods

Resistive switching devices having a switching layer and an intermediate electrode layer and methods of formation thereof

KAMALANATHAN DEEPAK

Circuits and methods for placing programmable impedance memory elements in high impedance states

Circuits and methods for placing programmable impedance memory elements in high impedance states

ADESTO TECH CORP

Resistive switching memory with cell access by analog signal controlled transmission gate

Resistive switching memory having a resistor, diode, and switch memory cell

LSI CORP

Shallow trench isolation structure with low trench parasitic capacitance

ORACLE AMERICA INC

Leakage power optimization considering gate input activity and timing slack

SUN MICROSYSTEMS INC

Scheme for screening weak memory cell

DICKINSON PAUL J

Technique for determining circuit interdependencies