Inventor

SASANKA RUCHIRA

US21 patents

⚠️ This page may combine multiple inventors who share the name “SASANKA RUCHIRA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SASANKA RUCHIRA

INTEL CORP

Opportunistic increase of ways in memory-side cache

Using control flow data structures to direct and track instruction execution

Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads

Method, apparatus, system for continuous automatic tuning of code regions

Continuous automatic tuning of code regions

Utilization of processor capacity at low operating frequencies

Apparatus and method to reduce bandwidth and latency overheads of probabilistic caches

Reducing conflicts in direct mapped caches

Reducing conflicts in direct mapped caches

Utilization of processor capacity at low operating frequencies

Apparatus and method for considering spatial locality in loading data elements for execution

Opportunistic increase of ways in memory-side cache

Instruction and logic for cache control operations

Utilization of processor capacity at low operating frequencies

Analyzing potential benefits of vectorization

Automatic identification and generation of non-temporal store and load operations in a dynamic optimization environment

Post-compile cache blocking analyzer

SASANKA RUCHIRA

Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads

System, apparatus and method for translating vector instructions

Method, apparatus, system creating, executing and terminating mini-threads

SAGER DAVID J

Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads