Inventor · disambiguated record
Peter J. Mcelheny
Also filed as: MCELHENY PETER · MCELHENY PETER J · MCELHENY PETER JOHN
42 granted patents·4 pending applications·558 citations·filing 1997–2020
98Inventor score
Top patents by PatentIndex Score
46 records- 0196US7348827B2Apparatus and methods for adjusting performance of programmable logic devicesALTERA CORP·Filed 2004·Granted Mar 25, 2008·58 cites·15 claims
- 0294US7741716B1Integrated circuit bond pad structuresALTERA CORP·Filed 2005·Granted Jun 22, 2010·36 cites·20 claims
- 0394US7129745B2Apparatus and methods for adjusting performance of integrated circuitsALTERA CORP·Filed 2004·Granted Oct 31, 2006·79 cites·9 claims
- 0494US7125760B1Method for implementing electro-static discharge protection in silicon-on-insulator devicesALTERA CORP·Filed 2005·Granted Oct 24, 2006·29 cites·10 claims
- 0594US6740944B1Dual-oxide transistors for the improvement of reliability and off-state leakageALTERA CORP·Filed 2002·Granted May 25, 2004·73 cites·20 claims
- 0693US8638594B1Integrated circuits with asymmetric transistorsSINHA SHANKAR·Filed 2011·Granted Jan 28, 2014·19 cites·20 claims
- 0793US8138786B2Apparatus and methods for adjusting performance of integrated circuitsLEWIS DAVID·Filed 2009·Granted Mar 20, 2012·17 cites·12 claims
- 0892US10291397B2Active interposer for localized programmable integrated circuit reconfigurationINTEL CORP·Filed 2016·Granted May 14, 2019·6 cites·11 claims
- 0991US11784794B2Active interposer for localized programmable integrated circuit reconfigurationINTEL CORP·Filed 2020·Granted Oct 10, 2023·2 cites·16 claims
- 1091US7573317B2Apparatus and methods for adjusting performance of integrated circuitsALTERA CORP·Filed 2006·Granted Aug 11, 2009·16 cites·28 claims
- 1188US8664725B1Strain enhanced transistors with adjustable layoutsVENKITACHALAM GIRISH·Filed 2011·Granted Mar 4, 2014·12 cites·18 claims
- 1287US9576617B1Multiport memory element circuitryALTERA CORP·Filed 2014·Granted Feb 21, 2017·9 cites·17 claims
- 1383US7639033B2On-chip voltage regulator using feedback on process/product parametersALTERA CORP·Filed 2006·Granted Dec 29, 2009·12 cites·15 claims
- 1482US7277346B1Method and system for hard failure repairs in the fieldALTERA CORP·Filed 2004·Granted Oct 2, 2007·34 cites·4 claims
- 1581US7759226B1Electrical fuse with sacrificial contactALTERA CORP·Filed 2005·Granted Jul 20, 2010·9 cites·3 claims
- 1678US6906387B1Method for implementing electro-static discharge protection in silicon-on-insulator devicesALTERA CORP·Filed 2003·Granted Jun 14, 2005·20 cites·10 claims
- 1774US9634094B1Strain-enhanced transistors with adjustable layoutsALTERA CORP·Filed 2014·Granted Apr 25, 2017·2 cites·7 claims
- 1872US8627264B1Automated verification of transformational operations on a photomask representationVENKITACHALAM GIRISH·Filed 2009·Granted Jan 7, 2014·5 cites·18 claims
- 1971US7107566B1Programmable logic device design tools with gate leakage reduction capabilitiesALTERA CORP·Filed 2004·Granted Sep 12, 2006·15 cites·10 claims
- 2069US7812408B1Integrated circuits with metal-oxide-semiconductor transistors having enhanced gate depletion layersALTERA CORP·Filed 2007·Granted Oct 12, 2010·4 cites·18 claims
- 2168US8057964B2Photolithographic reticles with electrostatic discharge protection structuresHSU CHE TA·Filed 2008·Granted Nov 15, 2011·2 cites·18 claims
- 2267US7235884B1Local control of electrical and mechanical properties of copper interconnects to achieve stable and reliable viaALTERA CORP·Filed 2003·Granted Jun 26, 2007·18 cites·8 claims
- 2366US7902611B1Integrated circuit well isolation structuresALTERA CORP·Filed 2007·Granted Mar 8, 2011·3 cites·12 claims
- 2464US7170308B1On-chip voltage regulator using feedback on process/product parametersALTERA CORP·Filed 2003·Granted Jan 30, 2007·11 cites·5 claims
- 2564US6951792B1Dual-oxide transistors for the improvement of reliability and off-state leakageALTERA CORP·Filed 2004·Granted Oct 4, 2005·8 cites·11 claims
- 2662US10778414B2Active interposer for localized programmable integrated circuit reconfigurationINTEL CORP·Filed 2019·Granted Sep 15, 2020·0 cites·13 claims
- 2762US9484411B1Integrated circuit and a method to optimize strain inducing compositesALTERA CORP·Filed 2014·Granted Nov 1, 2016·1 cites·11 claims
- 2857US8995177B1Integrated circuits with asymmetric transistorsALTERA CORP·Filed 2013·Granted Mar 31, 2015·1 cites·16 claims
- 2954US6187634B1Process for making an EEPROM active area castlingALTERA CORP·Filed 1998·Granted Feb 13, 2001·13 cites·11 claims
- 3053US6127217AMethod of forming highly resistive interconnectsALTERA CORP·Filed 1999·Granted Oct 3, 2000·19 cites·26 claims
- 3151US8755218B2Multiport memory element circuitryLEE SHIH-LIN S·Filed 2011·Granted Jun 17, 2014·1 cites·20 claims
- 3251US8130538B2Non-volatile memory circuit including voltage divider with phase change memory devicesMCELHENY PETER J·Filed 2009·Granted Mar 6, 2012·3 cites·25 claims
- 3351US6038171AField emission erasable programmable read-only memoryALTERA CORP·Filed 1997·Granted Mar 14, 2000·12 cites·33 claims
- 3449US6829127B1High performance capacitor structureALTERA CORP·Filed 2003·Granted Dec 7, 2004·4 cites·22 claims
- 3548US7514758B2Dual-oxide transistors for the improvement of reliability and off-state leakageALTERA CORP·Filed 2005·Granted Apr 7, 2009·0 cites·13 claims
- 3646US8765541B1Integrated circuit and a method to optimize strain inducing compositesVENKITACHALAM GIRISH·Filed 2011·Granted Jul 1, 2014·0 cites·17 claims
- 3745US2008164936A1Apparatus and Methods for Adjusting Performance of Programmable Logic DevicesALTERA CORP·Filed 2008·Application pending·0 cites
- 3844US8492798B1Electrical fuse with sacrificial contactLEE SHIH-LIN S·Filed 2010·Granted Jul 23, 2013·0 cites·2 claims
- 3943US6472272B1Castled active area maskALTERA CORP·Filed 2000·Granted Oct 29, 2002·1 cites·12 claims
- 4043US2015206965A1High performance finfetALTERA CORP·Filed 2014·Application pending·0 cites
- 4138US2017365643A1Parallel configured resistive memory elementsALTERA CORP·Filed 2016·Application pending·0 cites
- 4238US2007243492A1Double exposure photolithographic processMCELHENY PETER J·Filed 2007·Application pending·0 cites
- 4337US7045427B2Polysilicon gate doping level variation for reduced leakage currentALTERA CORP·Filed 2004·Granted May 16, 2006·0 cites·15 claims
- 4435US6750106B2Polysilicon gate doping level variation for reduced leakage currentALTERA CORP·Filed 2002·Granted Jun 15, 2004·0 cites·16 claims
- 4535US6624467B1EEPROM active area castlingALTERA CORP·Filed 2002·Granted Sep 23, 2003·0 cites·19 claims
- 4633US6265746B1Highly resistive interconnectsALTERA CORP·Filed 1999·Granted Jul 24, 2001·4 cites·15 claims
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