Inventor
TAN CHUNG KWANG
US4 patents
Patents
4 patentsUS11264307B2Mar 1, 2022
Dual-damascene zero-misalignment-via process for semiconductor packaging
INTEL CORP0 citations61
US11721631B2Aug 8, 2023
Via structures having tapered profiles for embedded interconnect bridge substrates
INTEL CORP0 citations59
US11373951B2Jun 28, 2022
Via structures having tapered profiles for embedded interconnect bridge substrates
INTEL CORP0 citations59
US10403564B2Sep 3, 2019
Dual-damascene zero-misalignment-via process for semiconductor packaging
INTEL CORP0 citations51