Inventor

KALYANASUNDHARAM VYDHYANATHAN

US81 patents

⚠️ This page may combine multiple inventors who share the name “KALYANASUNDHARAM VYDHYANATHAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KALYANASUNDHARAM VYDHYANATHAN

ADVANCED MICRO DEVICES INC

Shared resources in a chip multiprocessor

Core redundancy in a chip multiprocessor for highly reliable systems

Memory controller prioritization scheme

Processing node including a plurality of processor cores and an interconnect configurable in a test-mode to cause first and second transaction source indicators to be interchanged

Region based split-directory scheme to adapt to large cache sizes

Region based split-directory scheme to adapt to large cache sizes

Multi-node system low power management

Bandwidth matched scheduler

Compression of frequent data values across narrow links

Shared data fabric processing client reset system and method

Method and apparatus for in-band priority adjustment forwarding in a communication fabric

Cache prefetching with dynamic interleaving configuration modification

Speculative hint-triggered activation of pages in memory

Communicating between partitions in a statically partitioned multiprocessing system

Prefetching using a direct memory access engine

Dynamic memory reconfiguration

Shadow tag management for accelerator partitions

Tiered memory caching

Region based split-directory scheme to adapt to large cache sizes

Probe filter directory management

Technique to enable simultaneous use of on-die SRAM as cache and memory

Global addressing for switch fabric

Zero value memory compression

Dynamic memory reconfiguration

Low power cache

Region based directory scheme to adapt to large cache sizes

Home agent based cache transfer acceleration scheme

Region based directory scheme to adapt to large cache sizes

Light-weight memory expansion in a coherent memory system

Accelerating accesses to private regions in a region-based cache directory scheme

Home agent based cache transfer acceleration scheme

Caching policies for processing units on multiple sockets

Dynamic cache bypass for power savings

Method and apparatus for encoding erroneous data in an error correction code protected memory

Sparsity compression for increased cache capacity

Dynamically controlled cache rinsing

Coherent block read fulfillment

Dynamic buffer management in multi-client token flow control routers

System direct memory access engine offload

Coherent block read fulfillment

System direct memory access engine offload

Dynamic buffer management in multi-client token flow control routers

Allocation control for cache

Page rinsing scheme to keep a directory page in an exclusive state in a single complex

Multi-level cache coherency protocol for cache line evictions

FUJITSU LTD

Dynamic variable page size translation of addresses

Read port design and method for register array

GLOBALFOUNDRIES INC

Shared resources in a chip multiprocessor

Shared resources in a chip multiprocessor

HUGHES WILLIAM A

Processor power management and method