Inventor

BHARGAVA RAVINDRA N

US17 patents

⚠️ This page may combine multiple inventors who share the name “BHARGAVA RAVINDRA N”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BHARGAVA RAVINDRA N

ADVANCED MICRO DEVICES INC

Dynamic page state aware scheduling of read/write burst transactions

Dynamic per-bank and all-bank refresh

Speculative hint-triggered activation of pages in memory

Staging memory access requests

Region based directory scheme to adapt to large cache sizes

Region based directory scheme to adapt to large cache sizes

Dynamic page state aware scheduling of read/write burst transactions

Speculative hint-triggered activation of pages in memory

Mechanism to efficiently rinse memory-side cache of dirty data

Tag accelerator for low latency DRAM cache

Adaptive page close prediction

Cache to cache data transfer acceleration techniques

Variable distance bypass between tag array and data array pipelines in a cache

Thread selection at a processor based on branch prediction confidence

Cache control aware memory controller

SUGGS DAVID

Branch history with polymorphic indirect branch information

BHARGAVA RAVINDRA N

Detecting branch direction and target address pattern and supplying fetch address by replay unit instead of branch prediction unit