Inventor
S JAYAKRISHNA P
IN5 patents
⚠️ This page may combine multiple inventors who share the name “S JAYAKRISHNA P”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
4 patentsUS12079155B2Sep 3, 2024
Graphics processor operation scheduling for deterministic latency
INTEL CORP6 citations93
US12153541B2Nov 26, 2024
Cache structure and utilization
INTEL CORP0 citations73
US12093210B2Sep 17, 2024
Compression techniques
INTEL CORP1 citations72
US9471323B2Oct 18, 2016
System and method of using an atomic data buffer to bypass a memory location
INTEL CORP0 citations40