Inventor

TSUTSUMI MASANORI

JP56 patents

⚠️ This page may combine multiple inventors who share the name “TSUTSUMI MASANORI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TSUTSUMI MASANORI

SANDISK TECHNOLOGIES LLC

Three-dimensional memory device with self-aligned multi-level drain select gate electrodes

Method of suppressing epitaxial growth in support openings and three-dimensional memory device containing non-epitaxial support pillars in the support openings

Three-dimensional memory device containing source contact to bottom of vertical channels and method of making the same

Three-dimensional memory device with discrete self-aligned charge storage elements and method of making thereof

Three-dimensional memory device with different thickness insulating layers and method of making thereof

Three-dimensional memory device having select gate electrode that is thicker than word lines and method of making thereof

Three-dimensional memory device containing annular etch-stop spacer and method of making thereof

Three-dimensional memory device containing support pillars underneath a retro-stepped dielectric material and method of making thereof

Three-dimensional memory device with separated source-side lines and method of making the same

Three-dimensional memory device containing a carbon-doped source contact layer and methods for making the same

Three-dimensional memory device with gated contact via structures and method of making thereof

On-pitch drain select level isolation structure for three-dimensional memory device and method of making the same

Semiconductor die stacking using vertical interconnection by through-dielectric via structures and methods for making the same

Three-dimensional memory device with drain-select-level isolation structures and method of making the same

Three-dimensional memory device containing channels with laterally pegged dielectric cores

Three-dimensional memory device having a slimmed aluminum oxide blocking dielectric and method of making same

Three-dimensional memory device with a dielectric isolation spacer and methods of forming the same

Memory die with source side of three-dimensional memory array bonded to logic die and methods of making the same

Three-dimensional memory device with isolated source strips and method of making the same

Three-dimensional memory device with separated source-side lines and method of making the same

Memory die with source side of three-dimensional memory array bonded to logic die and methods of making the same

Three-dimensional memory devices containing memory stack structures with laterally separated charge storage elements and method of making thereof

Three-dimensional memory device containing vertically isolated charge storage regions and method of making thereof

Three-dimensional memory device containing amorphous and crystalline blocking dielectric layers

Three-dimensional memory device containing amorphous and crystalline blocking dielectric layers

Memory device with through-stack contact via structures which contact plural stacks and method of making the same

Three-dimensional memory device with separated source lines and method of making the same

Three-dimensional memory device and method of making thereof using double pitch word line formation

On-pitch drain select level isolation structure for three-dimensional memory device and method of making the same

Bonded assembly containing conductive via structures extending through word lines in a staircase region and methods for making the same

Bonded assembly containing conductive via structures extending through word lines in a staircase region and methods for making the same

Three-dimensional memory device containing epitaxial pedestals and top source contact

Three-dimensional memory device and method of making thereof using double pitch word line formation

SANDISK TECHNOLOGIES INC

Multi-charge region memory cells for a vertical NAND device

Bottom recess process for an outer blocking dielectric layer inside a memory opening

Method of making a three dimensional NAND device

Uniform thickness blocking dielectric portions in a three-dimensional memory structure

Batch contacts for multiple electrically conductive layers

Three-dimensional memory device containing an aluminum oxide etch stop layer for backside contact structure and method of making thereof

Three-dimensional memory device containing plural metal oxide blocking dielectric layers and method of making thereof

MATSUSHITA ELECTRIC INDUSTRIAL CO LTD

Standard cell for plural power supplies and related technologies

Electromagnetic disturbance analysis method and apparatus and semiconductor device manufacturing method using the method

Decoupling capacitors and semiconductor integrated circuit

Delay control circuit device, and a semiconductor integrated circuit device and a delay control method using said delay control circuit device

PANASONIC CORP

Semiconductor integrated circuit device and power source wiring method therefor

MOS transistor circuit

TDK CORP

Diplexer including two bandpass filters

Branching filter

FUJITSU SEMICONDUCTOR LTD

Method of manufacturing semiconductor device

SUZUKI MOTOR CO

Cover structure for exhaust manifold inlet ducts