Inventor
SATTIRAJU SESHU V
US4 patents
⚠️ This page may combine multiple inventors who share the name “SATTIRAJU SESHU V”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
LEE KEVIN J
2 patentsUS9142510B2Sep 22, 2015
3D interconnect structure comprising through-silicon vias combined with fine pitch backside metal redistribution lines fabricated using a dual damascene type approach
LEE KEVIN J17 citations90
US9449913B2Sep 20, 2016
3D interconnect structure comprising fine pitch single damascene backside metal redistribution lines combined with through-silicon vias
LEE KEVIN J18 citations82
INTEL CORP
2 patentsUS7064446B2Jun 20, 2006
Under bump metallization layer to enable use of high tin content solder bumps
INTEL CORP29 citations87
US9530740B2Dec 27, 2016
3D interconnect structure comprising through-silicon vias combined with fine pitch backside metal redistribution lines fabricated using a dual damascene type approach
INTEL CORP0 citations50