Inventor

DEVILLIERS ANTON

US75 patents

⚠️ This page may combine multiple inventors who share the name “DEVILLIERS ANTON”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DEVILLIERS ANTON

TOKYO ELECTRON LTD

Three-dimensional device and method of forming the same

Method and device for incorporating single diffusion break into nanochannel structures of FET devices

Three-dimensional semiconductor device including integrated circuit, transistors and transistor components and method of fabrication

Method and device for incorporating single diffusion break into nanochannel structures of FET devices

Three-dimensional semiconductor device and method of fabrication

Method for controlling transistor delay of nanowire or nanosheet transistor devices

Method for controlling transistor delay of nanowire or nanosheet transistor devices

Amelioration of global wafer distortion based on determination of localized distortions of a semiconductor wafer

Inline dispense capacitor

Method for recessing a fill material within openings formed on a patterned substrate

Power delivery network for CFET with buried power rails

Apparatus and method for simultaneous formation of diffusion break, gate cut, and independent N and P gates for 3D transistor devices

Highly regular logic design for efficient 3D integration

Method for forming and using stress-tuned silicon oxide films in semiconductor device patterning

3D directed self-assembly for nanostructures

Method for self-aligned double patterning without atomic layer deposition

Substrate backside texturing

Self-aligned method for vertical recess for 3D device integration

Highly regular logic design for efficient 3D integration

Method of manufacturing a semiconductor apparatus having stacked devices

Method of making 3D circuits with integrated stacked 3D metal lines for high density circuits

Semiconductor apparatus having stacked devices and method of manufacture thereof

Method of making 3D circuits with integrated stacked 3D metal lines for high density circuits

Method of forming gate spacer for nanowire FET device

Method of 3D logic fabrication to sequentially decrease processing temperature and maintain material thermal thresholds

Method for planarization of organic films

Critical dimension correction via calibrated trim dosing

Method of patterning a substrate using a sidewall spacer etch mask

Method of patterning a substrate using a sidewall spacer etch mask

Apparatus and method for wafer alignment

Reverse contact and silicide process for three-dimensional semiconductor devices

Replacement buried power rail in backside power delivery

DEVILLIERS ANTON

Methods of forming a masking pattern for integrated circuits

Epitaxial devices

Methods of forming structures supported by semiconductor substrates

Methods of forming patterns on substrates

Epitaxial growth method

Patterning mask and method of formation of mask using step double patterning

MICRON TECHNOLOGY INC

Methods of forming a masking pattern for integrated circuits

Method for epitaxial devices

Epitaxial devices

Methods of forming a pattern on a substrate

Epitaxial devices

SILLS SCOTT

Methods of fabricating substrates

Methods of fabricating substrates

Methods of fabricating substrates

Methods of fabricating substrates

ZHANG ZISHU

Methods of forming patterned masks

ZHOU JIANMING

Lithography methods, methods for forming patterning tools and patterning tools

LIGHT SCOTT

Reticle with composite polarizer and method of simultaneous optimization of imaging of a set of different patterns