Inventor

YOO CHANG SIK

KR65 patents

⚠️ This page may combine multiple inventors who share the name “YOO CHANG SIK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

YOO CHANG SIK

SAMSUNG ELECTRONICS CO LTD

Memory system having point-to-point bus configuration

Semiconductor memory systems, methods, and devices for controlling active termination

Output driver circuit for controlling up-slew rate and down-slew rate independently and up-driving strength and down-driving strength independently

Semiconductor memory device having different data rates in read operation and write operation

Delay locked looped circuits and methods of operation thereof

Synchronous semiconductor memory device having on-die termination circuit and on-die termination method

Memory system having stub bus configuration

Synchronous semiconductor memory device having on-die termination circuit and on-die termination method

Apparatus for ensuring correct start-up and phase locking of delay locked loop

Delay locked loops and methods that shift the phase of a delayed clock signal based on a reference phase value

Semiconductor memory device having different data rates in read operation and write operation

Integrated circuit memory devices that support selective mode register set commands and related methods

Methods of controlling memory modules that support selective mode register set commands

Integrated circuit memory devices that support selective mode register set commands and related memory modules, memory controllers, and methods

Circuit for generating a data strobe signal used in a double data rate synchronous semiconductor device

Duty cycle correction circuits that reduce distortion caused by mismatched transistor pairs

Apparatus and method for wireless power reception

Integrated circuit memory devices including mode registers set using a data input/output bus

Integrated circuit memory devices that support selective mode register set commands

Data output circuit and method in DDR synchronous semiconductor device

Methods of operating memory systems including memory devices set to different operating modes and related systems

Delay locked loop for controlling phase increase or decrease and phase control method thereof

Receiver circuit of semiconductor integrated circuit

Memory device with prefetched data ordering distributed in prefetched data path logic, circuit, and method of ordering prefetched data

Apparatus and method for charge control in wireless charging system

Ladder type clock network for reducing skew of clock signals

Synchronous semiconductor memory device having on-die termination circuit and on-die termination method

Subharmonic mixer capable of reducing noise and enhancing gain and linearlty

Quadrature voltage controlled oscillator

CMOS buffer circuit

Input buffer circuit for transforming pseudo differential signals into full differential signals

Apparatus and method for charging control in wireless charging system

UNIV HANYANG IND UNIV COOP FOUND

Transmitter for cancelling simultaneous switching noise and data transmission method in the same

Signal transmission device and method, and signal reception device

Phase-locked loop with high bandwidth using rising edge and falling edge of signal

High-speed data transmitting/receiving system and method of removing simultaneous switching noise and inter-symbol interference

System for linking and controlling terminals and user terminal used in the same

Method of adjusting an UI and user terminal using the same

HYNIX SEMICONDUCTOR INC

Clock data recovery apparatus

Open-loop digital duty cycle correction circuit without DLL

IUCF HYU

System for linking and controlling terminals and user terminal used in the same

Method of adjusting an UI and user terminal using the same

JEONG CHUN SEOK

Data equalizing circuit and data equalizing method

Data alignment circuit and method of semiconductor memory apparatus

SILICON MOTION INC

Re-configurable low noise amplifier utilizing feedback capacitors

SAMSUNG ELECTRO MECH

Phase shift circuit and power factor correction circuit including the same

PARK JAE-WOO

Communication apparatus and low noise amplifying method

YOO CHANG-SIK

Dual mode satellite signal receiver and method thereof

YANG JEONG MO

Power factor correction circuit for correcting power factor

ARABILITY IP LLC

Method of adjusting an UI and user terminal using the same