Inventor
LEE KEVIN J
US53 patents
⚠️ This page may combine multiple inventors who share the name “LEE KEVIN J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
35 patentsUS7391112B2Jun 24, 2008
Capping copper bumps
INTEL CORP91 citations98
US6943440B2Sep 13, 2005
Methods of processing thick ILD layers using spray coating or lamination for C4 wafer level thick metal integrated flow
INTEL CORP151 citations98
US6077337AJun 20, 2000
Chemical-mechanical polishing slurry
INTEL CORP80 citations96
US9041146B2May 26, 2015
Logic chip including embedded magnetic tunnel junctions
INTEL CORP30 citations93
US6346144B1Feb 12, 2002
Chemical-mechanical polishing slurry
INTEL CORP17 citations93
US6214098B1Apr 10, 2001
Chemical-mechanical polishing slurry
INTEL CORP29 citations93
US6384481B1May 7, 2002
Single step electroplating process for interconnect via fill and metal line patterning
INTEL CORP33 citations91
US6020266AFeb 1, 2000
Single step electroplating process for interconnect via fill and metal line patterning
INTEL CORP33 citations91
US7064446B2Jun 20, 2006
Under bump metallization layer to enable use of high tin content solder bumps
INTEL CORP29 citations87
US11469268B2Oct 11, 2022
Damascene-based approaches for embedding spin hall MTJ devices into a logic processor and the resulting structures
INTEL CORP8 citations86
US7964965B2Jun 21, 2011
Forming thick metal interconnect structures for integrated circuits
INTEL CORP14 citations84
US7088005B2Aug 8, 2006
Wafer stacking with anisotropic conductive adhesive
INTEL CORP12 citations84
US10290598B2May 14, 2019
Method and apparatus for forming backside die planar devices and saw filter
INTEL CORP7 citations83
US9997563B2Jun 12, 2018
Logic chip including embedded magnetic tunnel junctions
INTEL CORP8 citations83
US9660181B2May 23, 2017
Logic chip including embedded magnetic tunnel junctions
INTEL CORP7 citations83
US7498252B2Mar 3, 2009
Dual layer dielectric stack for microelectronics having thick metal lines
INTEL CORP8 citations82
US9716066B2Jul 25, 2017
Interconnect structure comprising fine pitch backside metal redistribution lines combined with vias
INTEL CORP16 citations77
US7732936B2Jun 8, 2010
Buffer coating having a physical mixture of high toughness polymer and a low shrinkage polymer
INTEL CORP6 citations74
US6984302B2Jan 10, 2006
Electroplating cell based upon rotational plating solution flow
INTEL CORP9 citations74
US11393873B2Jul 19, 2022
Approaches for embedding spin hall MTJ devices into a logic processor and the resulting structures
INTEL CORP2 citations73
US10811595B2Oct 20, 2020
Techniques for forming logic including integrated spin-transfer torque magnetoresistive random-access memory
INTEL CORP2 citations73
US10790263B2Sep 29, 2020
Integrated circuit die having backside passive components and methods associated therewith
INTEL CORP3 citations73
US10644064B2May 5, 2020
Logic chip including embedded magnetic tunnel junctions
INTEL CORP4 citations72
US9911689B2Mar 6, 2018
Through-body-via isolated coaxial capacitor and techniques for forming same
INTEL CORP3 citations72
US9721886B2Aug 1, 2017
Preservation of fine pitch redistribution lines
INTEL CORP5 citations67
US10224309B2Mar 5, 2019
Integrated circuit die having backside passive components and methods associated therewith
INTEL CORP1 citations63
US9252111B2Feb 2, 2016
Method for handling very thin device wafers
INTEL CORP2 citations63
US7982311B2Jul 19, 2011
Solder limiting layer for integrated circuit die copper bumps
INTEL CORP3 citations63
US7833899B2Nov 16, 2010
Multi-layer thick metallization structure for a microelectronic device, intergrated circuit containing same, and method of manufacturing an integrated circuit containing same
INTEL CORP2 citations63
US11037896B2Jun 15, 2021
Method and apparatus for forming backside die planar devices and saw filter
INTEL CORP0 citations62
US7585615B2Sep 8, 2009
Composite photoresist for modifying die-side bumps
INTEL CORP4 citations57
US7442634B2Oct 28, 2008
Method for constructing contact formations
INTEL CORP4 citations57
US9852964B2Dec 26, 2017
Through-body via formation techniques
INTEL CORP0 citations52
US6737360B2May 18, 2004
Controlled potential anodic etching process for the selective removal of conductive thin films
INTEL CORP1 citations52
US9530740B2Dec 27, 2016
3D interconnect structure comprising through-silicon vias combined with fine pitch backside metal redistribution lines fabricated using a dual damascene type approach
INTEL CORP0 citations50
LEE KEVIN J
6 patentsUS9142510B2Sep 22, 2015
3D interconnect structure comprising through-silicon vias combined with fine pitch backside metal redistribution lines fabricated using a dual damascene type approach
LEE KEVIN J17 citations90
US9489354B1Nov 8, 2016
Masking content while preserving layout of a webpage
LEE KEVIN J26 citations89
US8297605B2Oct 30, 2012
Multipurpose ball joint assembly and work holding devices
LEE KEVIN J26 citations89
US9449913B2Sep 20, 2016
3D interconnect structure comprising fine pitch single damascene backside metal redistribution lines combined with through-silicon vias
LEE KEVIN J18 citations82
US8994174B2Mar 31, 2015
Structure having a planar bonding surface
LEE KEVIN J3 citations63
US8910927B2Dec 16, 2014
Work holding device for an archery bow
LEE KEVIN J2 citations59
SENTISEARCH INC
3 patentsUS7238798B2Jul 3, 2007
Nucleic acids and proteins of insect Or83b odorant receptor genes and uses thereof
SENTISEARCH INC5 citations69
US7601829B2Oct 13, 2009
Nucleic acids and proteins of insect Or83b odorant receptor genes and uses thereof
SENTISEARCH INC1 citations58
US7550574B2Jun 23, 2009
Nucleic acids and proteins of insect Or83b odorant receptor genes and uses thereof
SENTISEARCH INC1 citations58
LONGYEAR CO
1 patentUNIV COLUMBIA
1 patentPAK POY & KNEEBONE PTY LTD
1 patentLIFE TECHNOLOGIES CORP
1 patentHE JUN
1 patentPELTO CHRISTOPHER M
1 patentShowing the top 50 of 53 patents by PatentIndex Score.