Inventor

THOMPTO BRIAN W

US126 patents

⚠️ This page may combine multiple inventors who share the name “THOMPTO BRIAN W”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

THOMPTO BRIAN W

IBM

Independent mapping of threads

Dynamic recalculation of resource vector at issue queue for steering of dependent instructions

Managing an issue queue for fused instructions and paired instructions in a microprocessor

Independent mapping of threads

Management of shared transactional resources

Dynamic management of a transaction retry indication

Multi-section garbage collection

Operation of a multi-slice processor with an expanded merge fetching queue

Generating ECC values for byte-write capable registers

Generating ECC values for byte-write capable registers

Operation of a multi-slice processor implementing simultaneous two-target loads and stores

Operation of a multi-slice processor implementing simultaneous two-target loads and stores

Handling and fusing load instructions in a processor

Instruction handling for accumulation of register results in a microprocessor

Check pointing of accumulator register results in a microprocessor

Handling unaligned load operations in a multi-slice computer processor

Managing an issue queue for fused instructions and paired instructions in a microprocessor

Out-of-order processor and method for back to back instruction issue

Prefetch performance

Techniques for dynamic sequential instruction prefetching

Handling unaligned load operations in a multi-slice computer processor

Managing a divided load reorder queue

Deterministic current based frequency optimization of processor chip

Deterministic current based frequency optimization of processor chip

Predicting and avoiding operand-store-compare hazards in out-of-order microprocessors

Systems and methods for dynamic control of a secure mode of operation in a processor

Prefetch store preallocation in an effective address-based cache directory

Program counter (PC)-relative load and store addressing for fused instructions

Fusion to enhance early address generation of load instructions in a microprocessor

Instruction chaining

Partial ECC mechanism for a byte-write capable register

Out-of-order processor that avoids deadlock in processing queues by designating a most favored instruction

Cache line replacement using reference states based on data reference attributes

Compute array of a processor with mixed-precision numerical linear algebra support

Compute array of a processor with mixed-precision numerical linear algebra support

Handling unaligned load operations in a multi-slice computer processor

Systems and methods for dynamic control of a secure mode of operation in a processor

Method and system for on demand control of hardware support for software pointer authentification in a computing system

Assignment of microprocessor register tags at issue time

Methods and systems for translating virtual addresses in a virtual memory based system

Loosely-coupled slice target file data

Dependency skipping in a load-compare-jump sequence of instructions by incorporating compare functionality into the jump instruction and auto-finishing the compare instruction

Inferring future value for speculative branch resolution in a microprocessor

Instruction handling for accumulation of register results in a microprocessor

Microprocessor that fuses load and compare instructions

Translating virtual addresses in a virtual memory based system

ALEXANDER GREGORY W

Predicting and avoiding operand-store-compare hazards in out-of-order microprocessors

Predicting and avoiding operand-store-compare hazards in out-of-order microprocessors

BUSABA FADI Y

Management of multiple nested transactions

GLOBALFOUNDRIES INC

Techniques for increasing vector processing utilization and efficiency through vector lane predication prediction