Inventor

BOERSMA MAARTEN J

DE46 patents

⚠️ This page may combine multiple inventors who share the name “BOERSMA MAARTEN J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BOERSMA MAARTEN J

IBM

Register files for storing data operated on by instructions of multiple widths

Register files for storing data operated on by instructions of multiple widths

Instruction handling for accumulation of register results in a microprocessor

Dynamic fusion based on operand size

Out-of-order processor that avoids deadlock in processing queues by designating a most favored instruction

Verification of a vector execution unit design

Instruction handling for accumulation of register results in a microprocessor

Thread-based organization of slice target register file entry in a microprocessor to permit writing scalar or vector data to portions of a single register file entry

Efficient forcing of corner cases in a floating point rounder

Low latency execution of floating-point record form instructions

On-the-fly adjustment of issue-write back latency to avoid write back collisions using a result buffer

Fast normalization in a mixed precision floating-point unit

Fast normalization in a mixed precision floating-point unit

Arithmetic logic unit for single-cycle fusion operations

Low-overhead, low-latency operand dependency tracking for instructions operating on register pairs in a processor core

Low-overhead, low-latency operand dependency tracking for instructions operating on register pairs in a processor core

Arithmetic logic unit for single-cycle fusion operations

ECC scrubbing method in a multi-slice microprocessor

Out-of-order processor that avoids deadlock in processing queues by designating a most favored instruction

ECC scrubbing in a multi-slice microprocessor

Splitable and scalable normalizer for vector data

Splitable and scalable normalizer for vector data

Fused multiply-adder with booth-encoding

Reversing processing order in half-pumped SIMD execution units to achieve K cycle issue-to-issue latency

Method to determine the oldest instruction in an instruction queue of a processor with multiple instruction threads

Banked slice-target register file for wide dataflow execution in a microprocessor

Verification of a vector execution unit design

Hardware-based implementation of secure hash algorithms

Low latency execution of floating-point record form instructions

Low latency execution of floating-point record form instructions

Cracked execution of move-to-FPSCR instructions

Determining an optimal path to search a branch target buffer

Method to execute successive dependent instructions from an instruction stream in a processor

Pipeline depth exploration in a register transfer level design description of an electronic circuit

BOERSMA MAARTEN J

Mechanism to speed-up multithreaded execution by register file write port reallocation

Normalizer shift prediction for log estimate instructions

Supporting multiple formats in a floating point processor

Reversing processing order in half-pumped SIMD execution units to achieve K cycle issue-to-issue latency

Method and data processing unit for calculating at least one multiply-sum of two carry-less multiplications of two input operands, data processing program and computer program product

Fast floating point compare with slower backup for corner cases

Apparatus and method for calculating an SHA-2 hash function in a general purpose processor

Fused multiply-adder with booth-encoding

Splitable and scalable normalizer for vector data

BAROWSKI HARRY S

Zero indication forwarding for floating point unit power reduction

Zero indication forwarding for floating point unit power reduction

ABERNATHY CHRISTOPHER M

Active power dissipation detection based on erroneus clock gating equations