Inventor

MOREIRA JOSE E

US60 patents

⚠️ This page may combine multiple inventors who share the name “MOREIRA JOSE E”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MOREIRA JOSE E

IBM

Hybrid method for event prediction and system control

Independent mapping of threads

Branch prediction using multiple versions of history data

Independent mapping of threads

Performing server migration and dependent server discovery in parallel

Counter-based wide fetch management

Method for providing high performance scalable file I/O through persistent file domain and functional partitioning

Hybrid event prediction and system control

Processor design for extended-precision arithmetic

Instruction handling for accumulation of register results in a microprocessor

Redundant transactions for detection of timing sensitive errors

Performing server migration and dependent server discovery in parallel

Compute array of a processor with mixed-precision numerical linear algebra support

Compute array of a processor with mixed-precision numerical linear algebra support

Counter-based wide fetch management

Branch prediction using multiple versions of history data

Transactions for checkpointing and reverse execution

Method and system for on demand control of hardware support for software pointer authentification in a computing system

Loosely-coupled slice target file data

Instruction handling for accumulation of register results in a microprocessor

Instruction fusion using dependence analysis

Independent mapping of threads

Efficient performance of inner loops on a multi-lane processor

Compressed indirect prediction caches

Reformatting matrices to improve computing efficiency

Encrypted data processing design including local buffers

Memory access operations for large graph analytics

Supporting large-word operations in a reduced instruction set computer (“RISC”) processor

Reformatting matrices to improve computing efficiency

Processor core design optimized for machine learning applications

Dispatching multiply and accumulate operations based on accumulator register index number

Three-dimensional lane predication for matrix operations

Program instruction scheduling

Converting multiple instructions into a single combined instruction with an extension opcode

Converting multiple instructions into a single combined instruction with an extension opcode

Independent mapping of threads

Page table including data fetch width indicator

Branch prediction using multiple versions of history data

Branch prediction using multiple versions of history data

Detection of hardware errors using periodically synchronized redundant transactions and comparing results from cores of a multi-core processor

Page table including data fetch width indicator

Page table including data fetch width indicator

Memory-area property storage including data fetch width indicator

Memory-area property storage including data fetch width indicator

Detection of hardware errors using redundant transactions for system test

Counter-based wide fetch management

EKANADHAM KATTAMURI

Operating a stack of information in an information handling system

Seamless interface for multi-threaded core accelerators

GLOBALFOUNDRIES INC

Techniques for increasing vector processing utilization and efficiency through vector lane predication prediction

CAIN III HAROLD W

Transactional memory system supporting unbroken suspended execution