Inventor

LE HUNG Q

US118 patents

⚠️ This page may combine multiple inventors who share the name “LE HUNG Q”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LE HUNG Q

IBM

Shared resource queue for simultaneous multithreading processing wherein entries allocated to different threads are capable of being interspersed among each other and a head pointer for one thread is capable of wrapping around its own tail in order to access a free entry

Independent mapping of threads

Fetch and store buffer that enables out-of-order execution of memory instructions in a data processing system

Dynamically shared group completion table between multiple threads

Dynamic recalculation of resource vector at issue queue for steering of dependent instructions

Managing an issue queue for fused instructions and paired instructions in a microprocessor

Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructions

Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructions

Independent mapping of threads

Split-level history buffer in a computer processing unit

Universal register rename mechanism for targets of different instruction types in a microprocessor

Completion table configured to track a larger number of outstanding instructions without increasing the size of the completion table

SMT flush arbitration

Operation of a multi-slice processor with an expanded merge fetching queue

Adaptive fetch gating in multithreaded processors, fetch control and method of controlling fetches

Instruction handling for accumulation of register results in a microprocessor

Check pointing of accumulator register results in a microprocessor

Handling unaligned load operations in a multi-slice computer processor

Managing an issue queue for fused instructions and paired instructions in a microprocessor

Split-level history buffer in a computer processing unit

Handling unaligned load operations in a multi-slice computer processor

Processing instructions in parallel with waw hazards and via a distributed history buffer in a microprocessor having a multi-execution slice architecture

Transactional storage accesses supporting differing priority levels

Detection of conflicts between transactions and page shootdowns

Dynamic update of the number of architected registers assigned to software threads using spill counts

COMPAQ COMPUTER CORP

Computer system and method for replacing obsolete or corrupt boot code contained within reprogrammable memory with new boot code supplied from an external source through a data port

Computer access via a single-use password

Flash ROM sharing between a processor and a controller

Multiple frequency phase-locked loop clock generator with stable transitions between frequencies

Flash ROM sharing between processor and microcontroller during booting and handling warm-booting events

Circuit and method employing feedback for driving a clocking signal to compensate for load-induced skew

Programmable memory device that supports multiple operational modes

Serial bus system for shadowing registers

Battery charger

Serial bus system for shadowing registers

Buffering digitizer data in a first-in first-out memory

COMPAQ INFORMATION TECHNOLOGIE

Apparatus and method for providing access security to a device coupled upon a two-wire bidirectional bus

Apparatus and method for maintaining secured access to relocated plug and play peripheral devices

Apparatus and method for programmably and flexibly assigning passwords to unlock devices of a computer system intended to remain secure

HEWLETT PACKARD DEVELOPMENT CO

Dynamically adaptive buffer mechanism

Dynamically adaptive buffer mechanism

(unassigned)

Flash ROM sharing between processor and microcontroller during booting and handling warm-booting events

GLOBALFOUNDRIES INC

Techniques for increasing vector processing utilization and efficiency through vector lane predication prediction

ABERNATHY CHRISTOPHER M

Thread transition management

EKANADHAM KATTAMURI

Seamless interface for multi-threaded core accelerators

HALL RONALD P

Hardware assist thread for increasing code parallelism

EMERSON THEODORE F

Memory subsystem having a first portion to store data with error correction code information and a second portion to store data without error correction code information

CAIN III HAROLD W

Transactional memory system supporting unbroken suspended execution

LE HUNG Q

Storing data in any of a plurality of buffers in a memory controller

APPLE INC

Techniques for firmware updates with accessories