Inventor

MUELLER SILVIA MELITTA

DE68 patents

⚠️ This page may combine multiple inventors who share the name “MUELLER SILVIA MELITTA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MUELLER SILVIA MELITTA

IBM

Floating point unit with fused multiply add and method for calculating a result with a floating point unit

Power saving in a floating point unit using a multiplier and aligner bypass

Enhanced low precision binary floating-point formatting

Floating point instruction with selectable comparison attributes

Power saving in FPU with gated power based on opcodes and data

High performance implementation of exponent adjustment in a floating point design

Protecting one-hot logic against short-circuits during power-on

Instruction handling for accumulation of register results in a microprocessor

Hybrid floating point representation for deep learning acceleration

Decimal load immediate instruction

Decimal floating point instructions to perform directly on compressed decimal floating point data

Perform sign operation decimal instruction

Decimal shift and divide instruction

Decimal load immediate instruction

Decimal scale and convert and split to hexadecimal floating point instruction

Shift amount correction for multiply-add

Apparatus and method for reducing the latency of sum-addressed shifters

Compute array of a processor with mixed-precision numerical linear algebra support

Compute array of a processor with mixed-precision numerical linear algebra support

High speed adder design for a multiply-add based floating point unit

Apparatus for controlling rounding modes in single instruction multiple data (SIMD) floating-point units

High throughput data flow for SHA-2 hashing module

Enhanced low precision binary floating-point formatting

Instruction handling for accumulation of register results in a microprocessor

Vector convert hexadecimal floating point to scaled decimal instruction

Hybrid floating point representation for deep learning acceleration

Condition code anticipator for hexadecimal floating point

Mixed precision floating-point multiply-add operation

Binary floating-point multiply and scale operation for compute-intensive numerical applications and apparatuses

Decimal load immediate instruction

Perform sign operation decimal instruction

Parallelized rounding for decimal floating point to binary coded decimal conversion

Efficient forcing of corner cases in a floating point rounder

Byte execution unit for carrying out byte instructions in a processor

Validating microprocessor performance

Leakage current reduction system and method

Parallel rounding for conversion from binary floating point to binary coded decimal

Three-dimensional lane predication for matrix operations

Floating point unit for exponential function implementation

Combined residue circuit protecting binary and decimal data

Decimal multiply and shift instruction

Combined residue circuit protecting binary and decimal data

Decimal shift and divide instruction

Decimal multiply and shift instruction

CARLOUGH STEVEN R

Range check based lookup tables

Decimal floating point mechanism and process of multiplication without resultant leading zero detection

Range check based lookup tables

DHONG SANG HOO

Method for controlling rounding modes in single instruction multiple data (SIMD) floating-point units

High speed adder design for a multiply-add based floating point unit

COWLISHAW MICHAEL F

Decimal floating-pointing quantum exception detection