Inventor

NGUYEN DUNG Q

US192 patents

⚠️ This page may combine multiple inventors who share the name “NGUYEN DUNG Q”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NGUYEN DUNG Q

IBM

Independent mapping of threads

Fetch and store buffer that enables out-of-order execution of memory instructions in a data processing system

Age based fast instruction issue

Method and system for restoring register mapper states for an out-of-order microprocessor

Dynamic recalculation of resource vector at issue queue for steering of dependent instructions

Register rename array with individual thread bits set upon allocation and cleared upon instruction completion

Redistribution of architected states for a processor register file

Managing an issue queue for fused instructions and paired instructions in a microprocessor

Independent mapping of threads

Split-level history buffer in a computer processing unit

Completion arbitration for more than two threads based on resource limitations

Adaptive allocation of reservation station entries to an instruction set with variable operands in a microprocessor

Universal register rename mechanism for targets of different instruction types in a microprocessor

Completion table configured to track a larger number of outstanding instructions without increasing the size of the completion table

SMT flush arbitration

Generating ECC values for byte-write capable registers

Generating ECC values for byte-write capable registers

Handling and fusing load instructions in a processor

Instruction handling for accumulation of register results in a microprocessor

Check pointing of accumulator register results in a microprocessor

Speculative execution of both paths of a weakly predicted branch instruction

Handling unaligned load operations in a multi-slice computer processor

Managing an issue queue for fused instructions and paired instructions in a microprocessor

Split-level history buffer in a computer processing unit

Processing instructions in parallel with waw hazards and via a distributed history buffer in a microprocessor having a multi-execution slice architecture

Handling unaligned load operations in a multi-slice computer processor

Bypassing a higher level register file in a processor having a multi-level register file and a set of bypass registers

Distributed history buffer flush and restore handling in a parallel slice design

Distributed history buffer flush and restore handling in a parallel slice design

Efficient usage of a multi-level register file utilizing a register file bypass

Program counter (PC)-relative load and store addressing for fused instructions

Fusion to enhance early address generation of load instructions in a microprocessor

Logical register recovery within a processor

Instruction chaining

Partial ECC mechanism for a byte-write capable register

In-pipe error scrubbing within a processor core

Determining of validity of speculative load data after a predetermined period of time in a multi-slice processor

Reducing power consumption in a multi-slice computer processor

Parity protection of a register

Age based fast instruction issue

Speculative finish of instruction execution in a processor core

Speculative finish of instruction execution in a processor core

Direct register restore mechanism for distributed history buffers

Speculative load data in byte-write capable register file and history buffer for a multi-slice microprocessor

Multi-slice processor issue of a dependent instruction in an issue queue based on issue of a producer instruction

Adaptive debug tracing for microprocessors

Handling unaligned load operations in a multi-slice computer processor

Split-level history buffer in a computer processing unit

BURKY WILLIAM E

Processor and method for partially flushing a dispatched instruction group including a mispredicted branch

ABERNATHY CHRISTOPHER M

Thread transition management