Inventor

PERIAMAN SHANGGAR

MY19 patents

⚠️ This page may combine multiple inventors who share the name “PERIAMAN SHANGGAR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PERIAMAN SHANGGAR

INTEL CORP

Stacked die semiconductor package

Stacked die package

Stacked-die packages with silicon vias and surface activated bonding

Multi-die semiconductor structure with intermediate vertical side chip and semiconductor package for same

Multi-die semiconductor structure with intermediate vertical side chip and semiconductor package for same

Package on package design to improve functionality and efficiency

Flexible system-in-package solutions for wearable devices

Flexible packaging architecture

Bandwidth allocation for network packet traffic

Stacked package assembly with voltage reference plane

Integrated circuit packaging techniques and configurations for small form-factor or wearable devices

Quality of service (QoS) processing of data packets

CHEAH BOK ENG

High-density inter-package connections for ultra-thin package-on-package structures, and processes of forming same

Method to enable controlled side chip interconnection for 3D integrated packaging system

Stacked die package

High density second level interconnection for bumpless build up layer (BBUL) packaging technology

PERIAMAN SHANGGAR

Die backside wire bond technology for single or stacked die package

Die backside metallization and surface activated bonding for stacked die packages

CHEW YEN HSIANG

Firmware verification using system memory error check logic