Inventor

CHOU CHIEN-CHIH

TW79 patents

⚠️ This page may combine multiple inventors who share the name “CHOU CHIEN-CHIH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHOU CHIEN-CHIH

TAIWAN SEMICONDUCTOR MFG CO LTD

High voltage integration for HKMG technology

Semiconductor structure and method of forming thereof

Semiconductor structure and method

Dishing prevention dummy structures for semiconductor devices

Dishing prevention dummy structures for semiconductor devices

Lateral MOSFET

Method and related apparatus for reducing gate-induced drain leakage in semiconductor devices

Thicker corner of a gate dielectric structure around a recessed gate electrode for an MV device

Semiconductor structure and method of forming thereof

High voltage integration for HKMG technology

Recessed composite capacitor

Dishing prevention dummy structures for semiconductor devices

Dishing prevention columns for bipolar junction transistors

High voltage integration for HKMG technology

Epitaxial source and drain structures for high voltage devices

Boundary region for high-k-metal-gate(HKMG) integration technology

Method and related apparatus for reducing gate-induced drain leakage in semiconductor devices

High voltage integration for HKMG technology

Semiconductor devices and methods of forming the same

Semiconductor structure and method of forming thereof

FUSI gated device formation

FUSI gated device formation

Semiconductor device and method of forming the same

Recessed gate for an MV device

Method and related apparatus for reducing gate-induced drain leakage in semiconductor devices

Method and related apparatus for reducing gate-induced drain leakage in semiconductor devices

Boundary region for high-k-metal-gate (HKMG) integration technology

FUSI gated device formation

High-voltage semiconductor devices and methods of formation

Semiconductor structure and forming method thereof

Semiconductor structure and method of forming the same

Method of forming a transistor device with a gate structure having a pair of recess regions and a resistive protection layer within

Semiconductor structure and method of forming thereof

Semiconductor structure and method of forming thereof

Thicker corner of a gate dielectric structure around a recessed gate electrode for an MV device

Dishing prevention dummy structures for semiconductor devices

Thicker corner of a gate dielectric structure around a recessed gate electrode for an MV device

High voltage LDMOS transistor and methods for manufacturing the same

Semiconductor structure and method of forming the same

Checkerboard dummy design for epitaxial open ratio

TAIWAN SEMICONDUCTOR MFG

Method for forming an improved low power SRAM contact

Method of forming integrated circuit having modified isolation structure

Method for forming an improved low power SRAM contact

High voltage device embedded non-volatile memory cell and fabrication method

Gate electrodes of HVMOS devices having non-uniform doping concentrations

Method of reducing NMOS device current degradation via formation of an HTO layer as an underlying component of a nitride-oxide sidewall spacer

Prevent defocus issue on wafer with tungsten coating on back-side

SU RU-YI

High voltage device having reduced on-state resistance

Gate electrodes of HVMOS devices having non-uniform doping concentrations

LIU HUEI-RU

Dummy structure for multiple gate dielectric interface and methods