Inventor

TUAN HSIAO-CHIN

TW57 patents

⚠️ This page may combine multiple inventors who share the name “TUAN HSIAO-CHIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TUAN HSIAO-CHIN

TAIWAN SEMICONDUCTOR MFG CO LTD

High voltage integration for HKMG technology

Through silicon via design for stacking integrated circuits

Through silicon via design for stacking integrated circuits

Through silicon via design for stacking integrated circuits

Method and related apparatus for reducing gate-induced drain leakage in semiconductor devices

Through silicon via design for stacking integrated circuits

High voltage integration for HKMG technology

High voltage integration for HKMG technology

Method and related apparatus for reducing gate-induced drain leakage in semiconductor devices

High voltage integration for HKMG technology

Memory devices and methods of manufacture thereof

Memory devices and methods of manufacture thereof

FUSI gated device formation

FUSI gated device formation

Recessed gate for an MV device

Self-aligned contact for trench MOSFET

Semiconductor device

Through silicon via design for stacking integrated circuits

Method and related apparatus for reducing gate-induced drain leakage in semiconductor devices

Method and related apparatus for reducing gate-induced drain leakage in semiconductor devices

Semiconductor structure and fabricating method thereof

Integrated chip including a device with a reduced surface field region

FUSI gated device formation

Method for forming an IC including a varactor with reduced surface field region

Semiconductor device and manufacturing method of the same

Memory devices and methods of manufacture thereof

Reduced surface field layer in varactor

Recessed gate for an MV device

Recessed gate for an MV device

Memory devices and methods of manufacture thereof

Memory devices and methods of manufacture thereof

IND TECH RES INST

Method for producing a roughened surface capacitor

Modified field isolation process with no channel-stop implant encroachment

Method of manufacturing low leakage and long retention time DRAM

Polysilicon undercut process for stack DRAM

Fabrication method to produce pit-free polysilicon buffer local oxidation isolation

Dual layer polysilicon capacitor node DRAM process

Dram peripheral circuit contact aspect ratio improvement process

CHENG CHIH-CHANG

Power MOSFETs and methods for forming the same

Quasi-vertical structure for high voltage MOS device

High voltage devices and methods of forming the high voltage devices

VANGUARD INT SEMICONDUCT CORP

Method for forming self-aligned contact with liner

Anti-reflection oxynitride film for polysilicon substrates

KALNITSKY ALEX

Power devices having reduced on-resistance and methods of their manufacture

Self-aligned contact for trench MOSFET

THEI KONG-BENG

Mechanism of forming SiC crystalline on Si substrates to allow integration of GaN and Si electronics

CHOU HSUEH-LIANG

Semiconductor device having multi-thickness gate dielectric

YAO CHIH-WEN

High voltage devices, systems, and methods for forming the high voltage devices

ETRON TECHNOLOGY INC

Fabrication method to produce pit-free polysilicon buffer local oxidation isolation

REN LIPING

Electrostatic discharge (ESD) protection circuit