Inventor

NAVON ARIEL

IL176 patents

⚠️ This page may combine multiple inventors who share the name “NAVON ARIEL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NAVON ARIEL

WESTERN DIGITAL TECH INC

Non-volatile memory data write management

Non-volatile memory with selective interleaved coding based on block reliability

System and method for performance-based multiple namespace resource allocation in a memory

Method and system for address table cache management based on correlation metric of first logical address and second logical address, wherein the correlation metric is incremented and decremented based on receive order of the first logical address and the second logical address

Memory health tracking for differentiated data recovery configurations

On-chip non-volatile memory (NVM) search

Storage device with increased endurance

System and method for predictive read of random data

System and method for scaling a historical pattern matching data structure in a memory device

Adaptive device quality of service by host memory buffer range

System and method for prediction of read commands to non-sequential data

Dynamic host memory allocation to a memory controller

Decoding optimization for channel mismatch

Parameterized iterative message passing decoder

Replacement data buffer pointers

ECC adjustment based on dynamic error information

Operating parameter offsets in solid state memory devices

Bandwidth allocation for storage system commands in peer-to-peer environment

Non-volatile memory die with on-chip data augmentation components for use with machine learning

Storage system and method for adaptive scheduling of background operations

Data storage device and method for dynamic prediction of random read with low memory consumption

Partial speed changes to improve in-order transfer

Parallel boot execution of memory devices

Detection of compromised storage device firmware

Solid state drive cache eviction policy by an unsupervised reinforcement learning scheme

Boosted boot procedure by background re-arrangement of read patterns

Power-endurance modes for data center solid-state drives

Optimizing data storage device operation by grouping logical block addresses and/or physical block addresses using hints

Storage device feature extraction optimization

Storage system and sorting-based method for random read command prediction in a multi-queue system

Zone-based device with control level selected by the host

Storage system and method for stream management in a multi-host virtualized storage system

Management operations in predictable latency mode

Non-volatile storage system with filtering of data samples for a monitored operational statistic

SANDISK TECHNOLOGIES INC

Updating read voltages using syndrome weight comparisons

Storage and retrieval of shaped data

Syndrome-based codeword decoding

Reading resistive random access memory based on leakage current

Dual polarity read operation

Methods for programming ReRAM devices

Error correction using multiple data sources

Data encoding techniques for a device

SANDISK TECHNOLOGIES LLC

Peak current management in non-volatile storage

Partially de-centralized latch management architectures for storage devices

Soft bit techniques for a data storage device

ECC decoder having adjustable parameters

Non-volatile memory configured to return error reduced read data

SHARON ERAN

Low density parity code (LDPC) decoding for memory with multiple log likelihood ratio (LLR) decoders

Fast detection of convergence or divergence in iterative decoding

NAVON ARIEL

Holders for portable memory cards and methods for manufacturing same