Inventor

HOSSAIN MASUM

CA63 patents

⚠️ This page may combine multiple inventors who share the name “HOSSAIN MASUM”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HOSSAIN MASUM

RAMBUS INC

Split-path equalizer and related methods, devices and systems

Clock recovery circuit

Clock recovery circuit

Clock and data recovery having shared clock generator

Split-path equalizer and related methods, devices and systems

Frequency-agile clock multiplier

Run-time output clock determination

Clock and data recovery having shared clock generator

Jitter-based clock selection

Low-latency, frequency-agile clock multiplier

Variable resolution digital equalization

PAM-4 DFE architectures with symbol-transition dependent DFE tap values

Direct digital sequence detector and equalizer based on analog-to-sequence conversion

Noise reducing receiver

Integrated circuit comprising circuitry to determine settings for an injection-locked oscillator

Wide range frequency synthesizer with quadrature generation and spur cancellation

Clock and data recovery having shared clock generator

Integrated circuit comprising fractional clock multiplication circuitry

Integrated circuit comprising circuitry to determine settings for an injection-locked oscillator

Integrated circuit comprising a delay-locked loop

Methods and circuits for decision-feedback equalization with early high-order-symbol detection

Symbol-rate phase detector for multi-PAM receiver

Variable resolution digital equalization

Symbol-rate phase detector for multi-PAM receiver

Collaborative clock and data recovery

Collaborative clock and data recovery

PAM-4 DFE architectures with symbol-transition dependent DFE tap values

Split-path equalizer and related methods, devices and systems

Split-path equalizer and related methods, devices and systems

Noise reducing receiver

Multi-mode clock multiplier

Methods and circuits for decision-feedback equalization with early high-order-symbol detection

Symbol-rate phase detector for multi-PAM receiver

Variable resolution digital equalization

PAM-4 DFE architectures with symbol-transition dependent DFE tap values

Direct digital sequence detection and equalization

Serial-link receiver using time-interleaved discrete time gain

PAM-4 DFE architectures with symbol-transition dependent DFE tap values

Variable resolution digital equalization

PAM-4 DFE architectures with symbol-transition dependent DFE tap values

Serial-link receiver using time-interleaved discrete time gain

Direct sequence detection and equalization

Variable resolution digital equalization

Clock and multi-valued data signaling

HOSSAIN MASUM

Integrated circuit comprising fractional clock multiplication circuitry

Clock and data recovery having shared clock generator

Wide range frequency synthesizer with quadrature generation and spur cancellation

ZERBE JARED L

Low-latency, frequency-agile clock multiplier

9011579 CANADA INCORPOREE

Collaborative analog-to-digital and time-to-delay conversion based on signal prediction

9011579 Canada Incorporée

Direct digital sequence detector and equalizer based on analog-to-sequence conversion