Inventor
APODACA MICHAEL
US109 patents
⚠️ This page may combine multiple inventors who share the name “APODACA MICHAEL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
48 patentsUS10893299B2Jan 12, 2021
Surface normal vector processing mechanism
INTEL CORP16 citations93
US10013734B1Jul 3, 2018
Programmable controller and command cache for graphics processors
INTEL CORP15 citations92
US11663746B2May 30, 2023
Systolic arithmetic on sparse data
INTEL CORP12 citations86
US10983594B2Apr 20, 2021
Sensory enhanced augmented reality and virtual reality device
INTEL CORP9 citations86
US11178373B2Nov 16, 2021
Adaptive resolution of point cloud and viewpoint prediction for video streaming in computing environments
INTEL CORP9 citations85
US10911799B2Feb 2, 2021
Video refinement mechanism
INTEL CORP13 citations85
US10846814B2Nov 24, 2020
Patch processing mechanism
INTEL CORP18 citations85
US11037269B1Jun 15, 2021
High-speed resume for GPU applications
INTEL CORP11 citations84
US10861126B1Dec 8, 2020
Asynchronous execution mechanism
INTEL CORP5 citations84
US10430147B2Oct 1, 2019
Collaborative multi-user virtual reality
INTEL CORP9 citations84
US10401954B2Sep 3, 2019
Sensory enhanced augmented reality and virtual reality device
INTEL CORP11 citations84
US10109078B1Oct 23, 2018
Controlling coarse pixel size from a stencil buffer
INTEL CORP5 citations84
US10699475B1Jun 30, 2020
Multi-pass apparatus and method for early termination of graphics shading
INTEL CORP10 citations83
US11829525B2Nov 28, 2023
Sensory enhanced augmented reality and virtual reality device
INTEL CORP4 citations75
US12425554B2Sep 23, 2025
Adaptive resolution of point cloud and viewpoint prediction for video streaming in computing environments
INTEL CORP1 citations74
US11869119B2Jan 9, 2024
Controlling coarse pixel size from a stencil buffer
INTEL CORP2 citations73
US11520555B2Dec 6, 2022
Collaborative multi-user virtual reality
INTEL CORP2 citations73
US11062506B2Jul 13, 2021
Tile-based immediate mode rendering with early hierarchical-z
INTEL CORP3 citations73
US10964091B2Mar 30, 2021
Augmented reality and virtual reality feedback enhancement system, apparatus and method
INTEL CORP2 citations73
US10930060B2Feb 23, 2021
Conditional shader for graphics
INTEL CORP2 citations73
US10733690B2Aug 4, 2020
GPU mixed primitive topology type processing
INTEL CORP2 citations73
US10706591B2Jul 7, 2020
Controlling coarse pixel size from a stencil buffer
INTEL CORP1 citations73
US10643374B2May 5, 2020
Positional only shading pipeline (POSH) geometry data processing with coarse Z buffer
INTEL CORP3 citations73
US10558496B2Feb 11, 2020
Techniques for accessing a graphical processing unit memory by an application
INTEL CORP4 citations73
US10242486B2Mar 26, 2019
Augmented reality and virtual reality feedback enhancement system, apparatus and method
INTEL CORP2 citations73
US10068307B2Sep 4, 2018
Command processing for graphics tile-based rendering
INTEL CORP2 citations73
US9916634B2Mar 13, 2018
Facilitating efficient graphics command generation and execution for improved graphics performance at computing devices
INTEL CORP2 citations73
US11284118B2Mar 22, 2022
Surface normal vector processing mechanism
INTEL CORP4 citations72
US10908865B2Feb 2, 2021
Collaborative multi-user virtual reality
INTEL CORP3 citations72
US10885880B2Jan 5, 2021
Programmable controller and command cache for graphics processors
INTEL CORP1 citations72
US10522114B2Dec 31, 2019
Programmable controller and command cache for graphics processors
INTEL CORP1 citations72
US11443406B2Sep 13, 2022
High-speed resume for GPU applications
INTEL CORP3 citations71
US10379611B2Aug 13, 2019
Virtual reality/augmented reality apparatus and method
INTEL CORP2 citations71
US10796397B2Oct 6, 2020
Facilitating dynamic runtime transformation of graphics processing commands for improved graphics performance at computing devices
INTEL CORP6 citations70
US10192281B2Jan 29, 2019
Graphics command parsing mechanism
INTEL CORP2 citations70
US10997772B1May 4, 2021
Dynamic constant update mechanism
INTEL CORP3 citations69
US11948017B2Apr 2, 2024
Thread modification to reduce command conversion latency
INTEL CORP2 citations68
US10552934B2Feb 4, 2020
Reducing memory latency in graphics operations
INTEL CORP2 citations65
US9881352B2Jan 30, 2018
Facilitating efficient graphics commands processing for bundled states at computing devices
INTEL CORP2 citations64
US12361600B2Jul 15, 2025
Systolic arithmetic on sparse data
INTEL CORP0 citations63
US11871142B2Jan 9, 2024
Synergistic temporal anti-aliasing and coarse pixel shading technology
INTEL CORP0 citations63
US11663774B2May 30, 2023
Anti-aliasing adaptive shader with pixel tile coverage raster rule system, apparatus and method
INTEL CORP0 citations63
US11636567B2Apr 25, 2023
Mutli-frame renderer
INTEL CORP0 citations63
US11302066B2Apr 12, 2022
Anti-aliasing adaptive shader with pixel tile coverage raster rule system, apparatus and method
INTEL CORP0 citations63
US11252370B2Feb 15, 2022
Synergistic temporal anti-aliasing and coarse pixel shading technology
INTEL CORP0 citations63
US11132759B2Sep 28, 2021
Mutli-frame renderer
INTEL CORP0 citations63
US10942740B2Mar 9, 2021
Transitionary pre-emption for virtual reality related contexts
INTEL CORP0 citations63
US10748234B2Aug 18, 2020
Reducing power for 3D workloads
INTEL CORP1 citations63
APODACA MICHAEL
2 patentsShowing the top 50 of 109 patents by PatentIndex Score.