Inventor
RAMESHAN NAVANEETH
CH16 patents
Patents
16 patentsUS11456867B2Sep 27, 2022
Trust-anchoring of cryptographic objects
IBM7 citations85
US10095621B1Oct 9, 2018
Coordination of cache and memory reservation
IBM11 citations82
US10545871B2Jan 28, 2020
Coordination of cache and memory reservation
IBM2 citations71
US11575508B2Feb 7, 2023
Unified HSM and key management service
IBM2 citations67
US12254092B2Mar 18, 2025
Attestation of logic loader code and integrity checking service logic code in a trusted execution environment (TEE)
IBM0 citations62
US12120097B2Oct 15, 2024
Authenticating key-value data pairs for protecting node related data
IBM0 citations62
US11689375B2Jun 27, 2023
Data in transit protection with exclusive control of keys and certificates across heterogeneous distributed computing environments
IBM1 citations62
US11416633B2Aug 16, 2022
Secure, multi-level access to obfuscated data for analytics
IBM1 citations61
US11265160B2Mar 1, 2022
Virtual memory extension layer for hardware security modules
IBM1 citations61
US10540285B2Jan 21, 2020
Coordination of cache and memory reservation
IBM0 citations51
US10318425B2Jun 11, 2019
Coordination of cache and memory reservation
IBM0 citations51
US12267421B2Apr 1, 2025
Post quantum secure ingress/egress network communication
IBM0 citations50
US11314739B2Apr 26, 2022
Dynamically slicing datastore query sizes
IBM0 citations50
US10931443B2Feb 23, 2021
Hierarchical key management based on bitwise XOR operations
IBM0 citations50
US12105985B2Oct 1, 2024
Processing data in-memory with memory devices having a crossbar array structure
IBM0 citations47
US10623183B2Apr 14, 2020
Postponing entropy depletion in key management systems with hardware security modules
IBM0 citations37