Inventor

YOO HUI JAE

US78 patents

⚠️ This page may combine multiple inventors who share the name “YOO HUI JAE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

YOO HUI JAE

INTEL CORP

Subtractive self-aligned via and plug patterning for back end of line (BEOL) interconnects

Conformal low temperature hermetic dielectric diffusion barriers

Scalable interconnect structures with selective via posts

Backside contacts for semiconductor devices

Subtractively patterned interconnect structures for integrated circuits

Interconnect wires including relatively low resistivity cores

Interconnects with fully clad lines

Methods for forming planarized hermetic barrier layers and structures formed thereby

Stacked forksheet transistors

Transistors, memory cells, and arrangements thereof

Gate-all-around integrated circuit structures having depopulated channel structures using multiple bottom-up oxidation approaches

Multi-chip module having a stacked logic chip and memory stack

III-V source/drain in top NMOS transistors for low temperature stacked transistor contacts

Stacked transistors with Si PMOS and high mobility thin film transistor NMOS

Interconnect wires including relatively low resistivity cores

Maskless air gap to prevent via punch through

Conformal low temperature hermetic dielectric diffusion barriers

Subtractively patterned interconnect structures for integrated circuits

Spin orbit torque (SOT) memory devices and their methods of fabrication

Bilayer memory stacking with computer logic circuits shared between bottom and top memory layers

Stacked backend memory with resistive switching devices

Method to fabricate metal and ferromagnetic metal multilayer interconnect line for skin effect suppression

Transistors stacked on front-end p-type transistors

Passivation layers for thin film transistors

Conformal low temperature hermetic dielectric diffusion barriers

Interconnect wires including relatively low resistivity cores

Sideways vias in isolation areas to contact interior layers in stacked devices

Forming an oxide volume within a fin

Stacked source-drain-gate connection and process for forming such

Conformal low temperature hermetic dielectric diffusion barriers

Multi-height and multi-width interconnect line metallization for integrated circuit structures

Passivation layers for thin film transistors and methods of fabrication

Sideways vias in isolation areas to contact interior layers in stacked devices

Stacked source-drain-gate connection and process for forming such

Interconnect wires including relatively low resistivity cores

Metallization structures for stacked device connectivity and their methods of fabrication

Compute near memory with backend memory

Capacitance reduction for semiconductor devices based on wafer bonding

Device including air gapping of gate spacers and other dielectrics and process for providing such

Forming an oxide volume within a fin

Vertically stacked memory elements with air gap

Conformal low temperature hermetic dielectric diffusion barriers

Stacked source-drain-gate connection and process for forming such

Two terminal spin orbit memory devices and methods of fabrication

Conformal low temperature hermetic dielectric diffusion barriers

Interconnect wires including relatively low resistivity cores

Transistors on heterogeneous bonding layers

KING SEAN

Conformal low temperature hermetic dielectric diffusion barriers

CHANDHOK MANISH

Method of creating a maskless air gap in back end interconnects with double self-aligned vias

YOO HUI JAE

Self-forming, self-aligned barriers for back-end interconnects and methods of making same