Inventor

VISWANATHAN NATARAJAN

US40 patents

⚠️ This page may combine multiple inventors who share the name “VISWANATHAN NATARAJAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

VISWANATHAN NATARAJAN

IBM

Latch clustering with proximity to local clock buffers

Structured placement of latches/flip-flops to minimize clock power in high-performance designs

Method to reduce the wirelength of analytical placement techniques by modulation of spreading forces vectors

Legalization of VLSI circuit placement with blockages using hierarchical row slicing

Boundary latch and logic placement to satisfy timing constraints

Post-placement cell shifting

Large cluster persistence during placement optimization of integrated circuit designs

Detailed routability by cell placement

Large cluster persistence during placement optimization of integrated circuit designs

Large cluster persistence during placement optimization of integrated circuit designs

Incremental timing optimization and placement

CADENCE DESIGN SYSTEMS INC

Modifying route topology to fix clock tree violations

Machine-learning based clustering for clock tree synthesis

Local cluster refinement

Region aware clustering

Balanced scaled-load clustering

Machine-learning based prediction method for iterative clustering during clock tree synthesis

Dynamic weighting scheme for local cluster refinement

Insertion delay and area tradeoff for buffering solution selection in clock tree synthesis

Hierarchically-aware buffering for clock structures

Grouping cells in cell library based on clustering

ALPERT CHARLES J

Placement of structured nets

Clock optimization with local clock buffer control optimization

Datapath placement using tiered assignment

Local objective optimization in global placement of an integrated circuit design

Post-placement cell shifting

Accuracy pin-slew mode for gate delay calculation

Element placement in circuit design based on preferred location

Separate refinement of local wirelength and local module density in intermediate placement of an integrated circuit design

Electronic design automation object placement with partially region-constrained objects

MAXIM INTEGRATED PRODUCTS

Method and apparatus for improving dynamic range of a touchscreen controller

Noise cancellation technique for capacitive touchscreen controller using differential sensing

JOHARAPURKAR ASHUTOSH RAVINDRA

Noise cancellation technique for capacitive touchscreen controller using differential sensing

Use of random sampling technique to reduce finger-coupled noise

AGARWAL KANAK BEHARI

Multi-patterning lithography aware cell placement in integrated circuit design

UNIV IOWA STATE RES FOUND INC

Fastplace method for integrated circuit design

GLOBALFOUNDRIES INC

Alignment net insertion for straightening the datapath in a force-directed placer

KIM MYUNG-CHUL

Alignment net insertion for straightening the datapath in a force-directed placer

ALPERT CHARLES JAY

Latch clustering with proximity to local clock buffers

QUALCOMM INC

Noise cancellation technique for capacitive touchscreen controller using differential sensing