Inventor
BAUTISTA EDWARD V
US3 patents
Patents
3 patentsUS6622274B1Sep 16, 2003
Method of micro-architectural implementation on bist fronted state machine utilizing ‘death logic’ state transition for area minimization
ADVANCED MICRO DEVICES INC21 citations89
US6891752B1May 10, 2005
System and method for erase voltage control during multiple sector erase of a flash memory device
ADVANCED MICRO DEVICES INC15 citations82
US6587982B1Jul 1, 2003
Method of micro-architectural implementation of interface between bist state machine and tester interface to enable bist cycling
ADVANCED MICRO DEVICES INC12 citations70