Inventor
HSU LI-CHUNG
TW29 patents
⚠️ This page may combine multiple inventors who share the name “HSU LI-CHUNG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
TAIWAN SEMICONDUCTOR MFG CO LTD
21 patentsUS11068637B1Jul 20, 2021
Systems and methods for context aware circuit design
TAIWAN SEMICONDUCTOR MFG CO LTD9 citations85
US11531802B2Dec 20, 2022
Layout context-based cell timing characterization
TAIWAN SEMICONDUCTOR MFG CO LTD5 citations83
US11853676B2Dec 26, 2023
Layout context-based cell timing characterization
TAIWAN SEMICONDUCTOR MFG CO LTD2 citations72
US12593497B2Mar 31, 2026
Integrated circuit in hybrid row height structure
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations62
US12369389B2Jul 22, 2025
Integrated circuit in hybrid row height structure
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations62
US12210811B2Jan 28, 2025
Layout context-based cell timing characterization
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations62
US12175180B2Dec 24, 2024
Systems and methods for context aware circuit design
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations62
US12074069B2Aug 27, 2024
Semiconductor device and integrated circuit in hybrid row height structure
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations62
US11816413B2Nov 14, 2023
Systems and methods for context aware circuit design
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations62
US11791213B2Oct 17, 2023
Integrated circuit in hybrid row height structure
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations62
US11355395B2Jun 7, 2022
Integrated circuit in hybrid row height structure
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations62
US9400866B2Jul 26, 2016
Layout modification method and system
TAIWAN SEMICONDUCTOR MFG CO LTD1 citations62
US11783106B2Oct 10, 2023
Circuit testing and manufacture using multiple timing libraries
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations60
US11003820B2May 11, 2021
Method of determining a worst case in timing analysis
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations60
US10977402B2Apr 13, 2021
Circuit testing and manufacture using multiple timing libraries
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations60
US10216879B1Feb 26, 2019
Method for establishing aging model of device and analyzing aging state of device with aging model
TAIWAN SEMICONDUCTOR MFG CO LTD1 citations58
US9122839B2Sep 1, 2015
Layout modification method and system
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations51
US10776545B2Sep 15, 2020
Method of determing a worst case in timing analysis
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations50
US10747924B2Aug 18, 2020
Method for manufacturing integrated circuit with aid of pattern based timing database indicating aging effect
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations50
US10503849B2Dec 10, 2019
Circuit testing and manufacture using multiple timing libraries
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations50
US10176284B2Jan 8, 2019
Semiconductor circuit design and manufacture method
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations40