Inventor
MORARKA SAURABH
US11 patents
⚠️ This page may combine multiple inventors who share the name “MORARKA SAURABH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
9 patentsUS10396201B2Aug 27, 2019
Methods of forming dislocation enhanced strain in NMOS structures
INTEL CORP1 citations71
US11411110B2Aug 9, 2022
Methods of forming dislocation enhanced strain in NMOS and PMOS structures
INTEL CORP0 citations61
US11107920B2Aug 31, 2021
Methods of forming dislocation enhanced strain in NMOS structures
INTEL CORP0 citations61
US11869987B2Jan 9, 2024
Gate-all-around integrated circuit structures including varactors
INTEL CORP0 citations60
US11417781B2Aug 16, 2022
Gate-all-around integrated circuit structures including varactors
INTEL CORP0 citations60
US11961836B2Apr 16, 2024
FinFET varactor quality factor improvement
INTEL CORP0 citations59
US12457778B2Oct 28, 2025
Conductive contacts wrapped around epitaxial source or drain regions
INTEL CORP0 citations57
US11515424B2Nov 29, 2022
Field-effect transistors with asymmetric gate stacks
INTEL CORP0 citations50
US12382721B2Aug 5, 2025
Integrated circuit structures having cut metal gates with dielectric spacer fill
INTEL CORP0 citations45