Inventor

SRINIVASAN DHEERAJ

US38 patents

⚠️ This page may combine multiple inventors who share the name “SRINIVASAN DHEERAJ”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SRINIVASAN DHEERAJ

MICRON TECHNOLOGY INC

Memory devices with four data line bias levels

Apparatuses and methods for automated dynamic word line start voltage

Data programming

Partially written superblock treatment

Memory device producing metadata characterizing applied read voltage level with respect to voltage distributions

Status polling based on die-generated pulsed signal

Resumption of program or erase operations in memory

Status polling based on die-generated pulsed signal

Memory status command aggregation

Resumption of program or erase operations in memory

Bitline driver isolation from page buffer circuitry in memory device

Checking status of multiple memory dies in a memory sub-system

Apparatuses and methods to control memory operations on buffers

Resumption of program or erase operations in memory

Data programming

Bitline driver isolation from page buffer circuitry in memory device

Apparatuses and methods for automated dynamic word line start voltage

Last written page searching

Partially written superblock treatment

Apparatuses and methods to control memory operations on buffers

Memory devices with four data line bias levels

Memory devices for suspend and resume operations

One check fail byte (CFBYTE) scheme

Cache management during execution of a program operation

Efficient cache program operation with data encoding

Memories for performing successive programming operations

Continuous memory programming operations

Apparatuses and methods to control memory operations on buffers

Apparatuses and methods for automated dynamic word line start voltage

Data programming

Independent plane architecture in a memory device

Boost voltage modulated corrective read

One check fail byte (CFBYTE) scheme

Multiple plane programming with quick plane programming termination and lagging plane boosting

Corrective reads implementing incremental reads with respect to adjacent wordlines

INTEL CORP

Methods and apparatus to program multi-level cell memory using target-only verify

Sense matching for hard and soft memory reads

Methods and apparatus to program multi-level cell memory using target-only verify