Inventor
REZEK JAMES E
US10 patents
Patents
10 patentsUS6684376B1Jan 27, 2004
Method and apparatus for selecting components within a circuit design database
UNISYS CORP205 citations98
US6516456B1Feb 4, 2003
Method and apparatus for selectively viewing nets within a database editor tool
UNISYS CORP77 citations95
US6701289B1Mar 2, 2004
Method and apparatus for using a placement tool to manipulate cell substitution lists
UNISYS CORP60 citations94
US5696693ADec 9, 1997
Method for placing logic functions and cells in a logic design using floor planning by analogy
UNISYS CORP89 citations94
US6910200B1Jun 21, 2005
Method and apparatus for associating selected circuit instances and for performing a group operation thereon
UNISYS CORP54 citations93
US7076410B1Jul 11, 2006
Method and apparatus for efficiently viewing a number of selected components using a database editor tool
UNISYS CORP25 citations92
US5912820AJun 15, 1999
Method and apparatus for distributing a clock tree within a hierarchical circuit design
UNISYS CORP38 citations92
US5956256ASep 21, 1999
Method and apparatus for optimizing a circuit design having multi-paths therein
UNISYS CORP47 citations91
US5819072AOct 6, 1998
Method of using a four-state simulator for testing integrated circuit designs having variable timing constraints
UNISYS CORP29 citations91
US5805861ASep 8, 1998
Method of stabilizing component and net names of integrated circuits in electronic design automation systems
UNISYS CORP45 citations89