Inventor
KANG TSUNG-SHENG
US35 patents
Patents
35 patentsUS11227922B2Jan 18, 2022
Sloped epitaxy buried contact
IBM6 citations75
US11271107B2Mar 8, 2022
Reduction of bottom epitaxy parasitics for vertical transport field effect transistors
IBM2 citations73
US11251182B2Feb 15, 2022
Staggered stacked vertical crystalline semiconducting channels
IBM2 citations73
US12588266B2Mar 24, 2026
CMOS integration for doped placeholder as direct backside contact
IBM0 citations62
US12568650B2Mar 3, 2026
Profile engineering for deep trenches in a semiconductor device
IBM0 citations62
US12557320B2Feb 17, 2026
FVBP without backside Si recess
IBM0 citations62
US12550620B2Feb 10, 2026
Top electrode to metal line connection for magneto-resistive random-access memory stack height reduction
IBM0 citations62
US12506049B2Dec 23, 2025
Transistors with backside source/drain contact and spacer
IBM0 citations62
US12482750B2Nov 25, 2025
Power distribution network with backside power rail
IBM0 citations62
US12484297B2Nov 25, 2025
Forksheet transistor with dual depth late cell boundary cut
IBM0 citations62
US12457780B2Oct 28, 2025
Semiconductor device with void under source/drain region for backside contact
IBM0 citations62
US12451412B2Oct 21, 2025
Backside gate via structure using self-aligned scheme
IBM0 citations62
US12446306B2Oct 14, 2025
Stacked field effect transistor structure with independent gate control between top and bottom gates
IBM0 citations62
US12396212B2Aug 19, 2025
Gate all-around device with through-stack nanosheet 2D channel
IBM0 citations62
US12324237B2Jun 3, 2025
Diffusion-break region in stacked-FET integrated circuit device
IBM0 citations62
US12310102B2May 20, 2025
Stacked vertical transport field-effect transistor logic gate structures with shared epitaxial layers
IBM0 citations62
US12266605B2Apr 1, 2025
Top via interconnects with line wiggling prevention
IBM0 citations62
US12262552B2Mar 25, 2025
Source/drain epitaxy process in stacked FET
IBM0 citations62
US12080640B2Sep 3, 2024
Self-aligned via to metal line for interconnect
IBM0 citations62
US12075627B2Aug 27, 2024
AI accelerator with MRAM, PCM, and recessed PCM bottom electrode
IBM0 citations62
US11956939B2Apr 9, 2024
Static random access memory using vertical transport field effect transistors
IBM0 citations62
US11942424B2Mar 26, 2024
Via patterning for integrated circuits
IBM0 citations62
US11849647B2Dec 19, 2023
Nonmetallic liner around a magnetic tunnel junction
IBM0 citations62
US11810918B2Nov 7, 2023
Stacked vertical transport field-effect transistor logic gate structures with shared epitaxial layers
IBM0 citations62
US11756961B2Sep 12, 2023
Staggered stacked vertical crystalline semiconducting channels
IBM0 citations62
US11678475B2Jun 13, 2023
Static random access memory using vertical transport field effect transistors
IBM0 citations62
US11652156B2May 16, 2023
Nanosheet transistor with asymmetric gate stack
IBM0 citations62
US11605673B2Mar 14, 2023
Dual resistive random-access memory with two transistors
IBM0 citations62
US11557675B2Jan 17, 2023
Reduction of bottom epitaxy parasitics for vertical transport field effect transistors
IBM0 citations62
US11251301B2Feb 15, 2022
Cross-bar vertical transport field effect transistors without corner rounding
IBM0 citations62
US11251288B2Feb 15, 2022
Nanosheet transistor with asymmetric gate stack
IBM0 citations62
US12538786B2Jan 27, 2026
Backside contact for semiconductor device
IBM0 citations52
US12453146B2Oct 21, 2025
Epi growth uniformity with source/drain placeholder
IBM0 citations52
US11562908B2Jan 24, 2023
Dielectric structure to prevent hard mask erosion
IBM0 citations52
US12550705B2Feb 10, 2026
Self-aligned backside gate contact
IBM0 citations51