Inventor
SATYANARAYANA BATCHU NAGA VENKATA
IN4 patents
Patents
4 patentsUS7669083B2Feb 23, 2010
System and method for re-shuffling test case instruction orders for processor design verification and validation
IBM22 citations89
US7797650B2Sep 14, 2010
System and method for testing SLB and TLB cells during processor design verification and validation
IBM14 citations82
US7747908B2Jun 29, 2010
System and method for creating different start cache and bus states using multiple test patterns for processor design verification and validation
IBM14 citations82
US8019566B2Sep 13, 2011
System and method for efficiently testing cache congruence classes during processor design verification and validation
IBM1 citations51