Inventor
COSTRINI GREGORY
US31 patents
⚠️ This page may combine multiple inventors who share the name “COSTRINI GREGORY”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
25 patentsUS8008095B2Aug 30, 2011
Methods for fabricating contacts to pillar structures in integrated circuits
IBM56 citations98
US6187680B1Feb 13, 2001
Method/structure for creating aluminum wirebound pad on copper BEOL
IBM353 citations96
US7001783B2Feb 21, 2006
Mask schemes for patterning magnetic tunnel junctions
IBM58 citations95
US6743642B2Jun 1, 2004
Bilayer CMP process to improve surface roughness of magnetic stack in MRAM technology
IBM37 citations92
US6323127B1Nov 27, 2001
Capacitor formed with Pt electrodes having a 3D cup-like shape with roughened inner and outer surfaces
IBM21 citations92
US6985384B2Jan 10, 2006
Spacer integration scheme in MRAM technology
IBM41 citations91
US6333559B1Dec 25, 2001
Method/structure for creating aluminum wirebound pad on copper BEOL
IBM41 citations90
US9431395B2Aug 30, 2016
Protection of semiconductor-oxide-containing gate dielectric during replacement gate formation
IBM7 citations84
US7875550B2Jan 25, 2011
Method and structure for self-aligned device contacts
IBM7 citations84
US7605447B2Oct 20, 2009
Highly manufacturable SRAM cells in substrates with hybrid crystal orientation
IBM12 citations84
US6686296B1Feb 3, 2004
Nitrogen-based highly polymerizing plasma process for etching of organic materials in semiconductor manufacturing
IBM13 citations83
US7884396B2Feb 8, 2011
Method and structure for self-aligned device contacts
IBM5 citations74
US5587045ADec 24, 1996
Gettering of particles from an electro-negative plasma with insulating chuck
IBM8 citations74
US4933302AJun 12, 1990
Formation of laser mirror facets and integration of optoelectronics
IBM14 citations74
US9577068B2Feb 21, 2017
Protection of semiconductor-oxide-containing gate dielectric during replacement gate formation
IBM2 citations73
US7097777B2Aug 29, 2006
Magnetic switching device
IBM9 citations73
US6974770B2Dec 13, 2005
Self-aligned mask to reduce cell layout area
IBM10 citations73
US6319840B1Nov 20, 2001
For mol integration
IBM12 citations73
US7871893B2Jan 18, 2011
Method for non-selective shallow trench isolation reactive ion etch for patterning hybrid-oriented devices compatible with high-performance highly-integrated logic devices
IBM4 citations63
US7470615B2Dec 30, 2008
Semiconductor structure with self-aligned device contacts
IBM3 citations63
US7923840B2Apr 12, 2011
Electrically conductive path forming below barrier oxide layer and integrated circuit
IBM1 citations52
US5843800ADec 1, 1998
Gettering of particles from an electro-negative plasma with insulating chuck
IBM1 citations52
US10177154B2Jan 8, 2019
Structure and method to prevent EPI short between trenches in FinFET eDRAM
IBM0 citations51
US9818741B2Nov 14, 2017
Structure and method to prevent EPI short between trenches in FINFET eDRAM
IBM0 citations51
US8039888B2Oct 18, 2011
Conductive spacers for semiconductor devices and methods of forming
IBM0 citations51
INFINEON TECHNOLOGIES AG
3 patentsUS6812141B1Nov 2, 2004
Recessed metal lines for protective enclosure in integrated circuits
INFINEON TECHNOLOGIES AG39 citations92
US6680500B1Jan 20, 2004
Insulating cap layer and conductive cap layer for semiconductor devices with magnetic material layers
INFINEON TECHNOLOGIES AG18 citations83
US7374952B2May 20, 2008
Methods of patterning a magnetic stack of a magnetic memory cell and structures thereof
INFINEON TECHNOLOGIES AG16 citations81