Inventor

WISE RICHARD S

US55 patents

⚠️ This page may combine multiple inventors who share the name “WISE RICHARD S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WISE RICHARD S

IBM

Metal oxide field effect transistor with a sharp halo

Process for finFET spacer formation

Method for reducing line edge roughness of oxide material using chemical oxide removal

Retrograde openings in thin films

Hard mask process to prevent surface roughness for selective dielectric etching

Integrated circuit having air gaps between dielectric and conducting lines

Baffle plate design for decreasing conductance lost during precipitation of polymer precursors in plasma etching chambers

Protective trench layer and gate spacer in finFET devices

Protection of semiconductor-oxide-containing gate dielectric during replacement gate formation

Graphene sacrificial deposition layer on beol copper liner-seed for mitigating queue-time issues between liner and plating step

Nitrogen based plasma process for metal gate MOS device

Nitrogen-based highly polymerizing plasma process for etching of organic materials in semiconductor manufacturing

Dual metal and dual dielectric integration for metal high-k FETs

In-situ plasma etch for TERA hard mask materials

Dual epitaxy CMOS processing using selective nitride formation for reduced gate pitch

Protection of semiconductor-oxide-containing gate dielectric during replacement gate formation

Asymmetric spacers

High selectivity nitride removal process based on selective polymer deposition

High selectivity nitride removal process based on selective polymer deposition

High-density plasma, organic anti-reflective coating etch system compatible with sensitive photoresist materials

Self-limited metal recess for deep trench metal fill

Metal oxide field effect transistor with a sharp halo and a method of forming the transistor

Wiring structure for integrated circuit with reduced intralevel capacitance

Silicon precursors for deep trench silicon etch processes

Amplification method for photoresist exposure in semiconductor chip manufacturing

Selective nitride: oxide anisotropic etch process

High selectivity nitride removal process based on selective polymer deposition

Liner protection in deep trench etching

Amplification method for photoresist exposure in semiconductor chip manufacturing

Dual epitaxy CMOS processing using selective nitride formation for reduced gate pitch

Method for controlling the profile of an etched metallic layer

Method for controlling the profile of an etched metallic layer

Patterning through imprinting

Method of patterning multilayer metal gate structures for CMOS devices

Method of processing wafers with resonant heating

High selectivity nitride removal process based on selective polymer deposition

Non-destructive in-situ elemental profiling

Edge protection seal for bonded substrates

LABONTE ANDRE P

Alignment tolerant semiconductor contact and method

Integrated circuit contact structure and method

RAMACHANDRAN RAVIKUMAR

Self-aligned contact for replacement gate devices

GLOBALFOUNDRIES INC

Self-aligned contact for replacement gate devices

LI ZHENGWEN

Etch stop layer formation in metal gate process

ENGEL BRETT H

Converting metal mask to metal-oxide etch stop layer and related semiconductor structure

YANG DAEWON

Method and apparatus for angular high density plasma chemical vapor deposition

CHUDZIK MICHAEL P

Dual metal and dual dielectric integration for metal high-K FETs

FAROOQ MUKTA G

Edge protection seal for bonded substrates

HICHRI HABIB

Method for simultaneously forming features of different depths in a semiconductor substrate

KHARE MUKESH V

Protecting exposed metal gate structures from etching processes in integrated circuit manufacturing

GLOBALFOUNDRIES SG PTE LTD

ARC residue-free etching