Inventor

UCHIYAMA KUNIO

US73 patents

⚠️ This page may combine multiple inventors who share the name “UCHIYAMA KUNIO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

UCHIYAMA KUNIO

HITACHI LTD

Semiconductor integrated circuit and design method and manufacturing method of the same

Semiconductor integrated circuit device having power reduction mechanism

Semiconductor integrated circuit device having power reduction mechanism

Data processor and data processing system having two translation lookaside buffers

Semiconductor integrated circuit device having power reduction mechanism

Semiconductor integrated circuit device having power reduction mechanism

Semiconductor integrated circuit device having power reduction mechanism

Processor system using synchronous dynamic memory

Single-chip-cache-buffer for selectively writing write-back and exclusively writing data-block portions to main-memory based upon indication of bits and bit-strings respectively

Microprocessor capable of stopping its operation at any cycle time

Content addressable memory having dual access modes

Multiprocessor cache system having three states for generating invalidating signals upon write accesses

Semiconductor device

Semiconductor integrated circuit device

Semiconductor integrated circuit device having power reduction mechanism

Semiconductor integrated circuit device

Semiconductor integrated circuit device having power reduction mechanism

Semiconductor integrated circuit device having power reduction

Semiconductor integrated circuit device having power reduction mechanism

Data processor with the ability of fast partial clearing of buffer memory

Data processor having an execution unit controlled by an instruction decoder and a microprogram ROM

Semiconductor memory device for performing parallel operations on hierarchical data lines

Data processor having two instruction registers connected in cascade and two instruction decoders

System for reexecuting branch instruction without fetching by storing target instruction control information

Data processor and data processor system having multiple modes of address indexing and operation

Semiconductor integrated circuit and method for manufacturing the same

Branching system for return from subroutine using target address in return buffer accessed based on branch type information in BHT

Microprocessor capable of decoding two instructions in parallel

Multi-processor system for invalidating hierarchical cache

Single chip cache with partial-write circuit for transferring a preselected portion of data between memory and buffer register

Multi-processing system and cache apparatus for use in the same

Semiconductor integrated circuit device

Semiconductor integrated circuit device having power reduction mechanism

Processor system using synchronous dynamic memory

Semiconductor integrated circuit device having power reduction mechanism

Single chip pipeline data processor using instruction and operand cache memories for parallel operation of instruction control and executions unit

Data processing system which selectively bypasses a cache memory in fetching information based upon bit information of an instruction

Semiconductor integrated circuit device having power reduction mechanism

RENESAS TECH CORP

Processor for controlling substrate biases in accordance to the operation modes of the processor

Semiconductor integrated circuit device having power reduction mechanism

Semiconductor integrated circuit device having power reduction mechanism

Processor system using synchronous dynamic memory

Substrate bias switching unit for a low power processor

Processor system using synchronous dynamic memory

Processor system using synchronous dynamic memory

RENESAS ELECTRONICS CORP

Substrate bias switching unit for a low power processor

Substrate bias switching unit for a low power processor

HITACHI MICRO SYSTEMS INC

Floating point unit pipeline synchronized with processor pipeline

UCHIYAMA KUNIO

Processor system using synchronous dynamic memory

HORIGUCHI MASASHI

Semiconductor integrated circuit device having power reduction mechanism