Inventor

NISHIMUKAI TADAHIKO

JP36 patents

Patents

36 patents

US5430397AJul 4, 1995

Intra-LSI clock distribution circuit

HITACHI LTD99 citations96

US5375215ADec 20, 1994

Multiprocessor system having shared memory divided into a plurality of banks with access queues corresponding to each bank

HITACHI LTD74 citations96

US5202969AApr 13, 1993

Single-chip-cache-buffer for selectively writing write-back and exclusively writing data-block portions to main-memory based upon indication of bits and bit-strings respectively

HITACHI LTD78 citations96

US4720811AJan 19, 1988

Multiprocessor system having a processor invalidating operand cache when lock-accessing

HITACHI LTD25 citations93

US5442229AAug 15, 1995

Metal lead-film carrier assembly having a plurality of film carriers, and film carrier-semiconductor chip assembly and semiconductor device containing such metal lead-film carrier assembly

HITACHI LTD24 citations93

US5381531AJan 10, 1995

Data processor for selective simultaneous execution of a delay slot instruction and a second subsequent instruction the pair following a conditional branch instruction

HITACHI LTD24 citations93

US5253197AOct 12, 1993

Semiconductor associative memory device with current sensing

HITACHI LTD24 citations93

US4912635AMar 27, 1990

System for reexecuting branch instruction without fetching by storing target instruction control information

HITACHI LTD30 citations93

US5269007ADec 7, 1993

RISC system capable of simultaneously executing data interlocked shift and arithmetic/logic instructions in one clock cycle by bypassing register

HITACHI LTD29 citations92

US5146573ASep 8, 1992

Single chip cache with partial-write circuit for transferring a preselected portion of data between memory and buffer register

HITACHI LTD31 citations92

US4845614AJul 4, 1989

Microprocessor for retrying data transfer

HITACHI LTD40 citations92

US4989140AJan 29, 1991

Single chip pipeline data processor using instruction and operand cache memories for parallel operation of instruction control and executions unit

HITACHI LTD21 citations82

US4942521AJul 17, 1990

Microprocessor with a cache memory in which validity flags for first and second data areas are simultaneously readable

HITACHI LTD21 citations82

US4937738AJun 26, 1990

Data processing system which selectively bypasses a cache memory in fetching information based upon bit information of an instruction

HITACHI LTD22 citations82

US5148526ASep 15, 1992

Data processing system with an enhanced cache memory control

HITACHI LTD11 citations81

US6272596B1Aug 7, 2001

Data processor

HITACHI LTD3 citations74

US5206945AApr 27, 1993

Single-chip pipeline processor for fetching/flushing instruction/data caches in response to first/second hit/mishit signal respectively detected in corresponding to their logical addresses

HITACHI LTD15 citations74

US5148532ASep 15, 1992

Pipeline processor with prefetch circuit

HITACHI LTD19 citations74

US4803616AFeb 7, 1989

Buffer memory

HITACHI LTD9 citations74

US4797816AJan 10, 1989

Virtual memory supported processor having restoration circuit for register recovering

HITACHI LTD10 citations74

US6381680B1Apr 30, 2002

Data processing system with an enhanced cache memory control

HITACHI LTD3 citations73

US5822761AOct 13, 1998

Data processing system which controls operation of cache memory based and the address being accessed

HITACHI LTD3 citations73

US5619677AApr 8, 1997

Data processing system with an enhanced cache memory control

HITACHI LTD3 citations73

US5509133AApr 16, 1996

Data processing system with an enhanced cache memory control

HITACHI LTD6 citations73

US5165086ANov 17, 1992

Microprocessor chip using two-level metal lines technology

HITACHI LTD8 citations72

US5974533AOct 26, 1999

Data processor

HITACHI LTD1 citations63

US5809274ASep 15, 1998

Purge control for ON-chip cache memory

HITACHI LTD2 citations63

US5349672ASep 20, 1994

Data processor having logical address memories and purge capabilities

HITACHI LTD3 citations63

US5129075AJul 7, 1992

Data processor with on-chip logical addressing and off-chip physical addressing

HITACHI LTD2 citations63

US5502825AMar 26, 1996

Data processing system with an enhanced cache memory control

HITACHI LTD2 citations62

US5479625ADec 26, 1995

Ring systolic array system for synchronously performing matrix/neuron computation using data transferred through cyclic shift register connected in cascade of trays

HITACHI LTD2 citations62

US6779102B2Aug 17, 2004

Data processor capable of executing an instruction that makes a cache memory ineffective

HITACHI LTD0 citations52

US5680631AOct 21, 1997

Data processor with on-chip cache memory and purge controller responsive to external signal for controlling access to the cache memory

HITACHI LTD0 citations52

NISHIMUKAI TADAHIKO

Patents

Intra-LSI clock distribution circuit

Multiprocessor system having shared memory divided into a plurality of banks with access queues corresponding to each bank

Single-chip-cache-buffer for selectively writing write-back and exclusively writing data-block portions to main-memory based upon indication of bits and bit-strings respectively

Microprocessor capable of stopping its operation at any cycle time

Content addressable memory having dual access modes

Multiprocessor system having distinct data bus and address bus arbiters

Multiprocessor system having a processor invalidating operand cache when lock-accessing

Metal lead-film carrier assembly having a plurality of film carriers, and film carrier-semiconductor chip assembly and semiconductor device containing such metal lead-film carrier assembly

Data processor for selective simultaneous execution of a delay slot instruction and a second subsequent instruction the pair following a conditional branch instruction

Semiconductor associative memory device with current sensing

System for reexecuting branch instruction without fetching by storing target instruction control information

RISC system capable of simultaneously executing data interlocked shift and arithmetic/logic instructions in one clock cycle by bypassing register

Single chip cache with partial-write circuit for transferring a preselected portion of data between memory and buffer register

Microprocessor for retrying data transfer

Single chip pipeline data processor using instruction and operand cache memories for parallel operation of instruction control and executions unit

Microprocessor with a cache memory in which validity flags for first and second data areas are simultaneously readable

Data processing system which selectively bypasses a cache memory in fetching information based upon bit information of an instruction

Data processing system with an enhanced cache memory control

Data processor

Single-chip pipeline processor for fetching/flushing instruction/data caches in response to first/second hit/mishit signal respectively detected in corresponding to their logical addresses

Pipeline processor with prefetch circuit

Buffer memory

Virtual memory supported processor having restoration circuit for register recovering

Data processing system with an enhanced cache memory control

Data processing system which controls operation of cache memory based and the address being accessed

Data processing system with an enhanced cache memory control

Data processing system with an enhanced cache memory control

Microprocessor chip using two-level metal lines technology

Data processor

Purge control for ON-chip cache memory

Data processor having logical address memories and purge capabilities

Data processor with on-chip logical addressing and off-chip physical addressing

Data processing system with an enhanced cache memory control

Ring systolic array system for synchronously performing matrix/neuron computation using data transferred through cyclic shift register connected in cascade of trays

Data processor capable of executing an instruction that makes a cache memory ineffective

Data processor with on-chip cache memory and purge controller responsive to external signal for controlling access to the cache memory