Inventor
RAO KALIPATNAM V
US11 patents
Patents
11 patentsUS4874716AOct 17, 1989
Process for fabricating integrated circuit structure with extremely smooth polysilicone dielectric interface
TEXAS INSTRUMENTS INC64 citations95
US5298451AMar 29, 1994
Recessed and sidewall-sealed poly-buffered LOCOS isolation methods
TEXAS INSTRUMENTS INC45 citations92
US5294563AMar 15, 1994
Sidewall-sealed and sandwiched poly-buffered locos isolation methods
TEXAS INSTRUMENTS INC31 citations92
US5369051ANov 29, 1994
Sidewall-sealed poly-buffered LOCOS isolation
TEXAS INSTRUMENTS INC33 citations89
US5159428AOct 27, 1992
Sidewall-sealed poly-buffered LOCOS isolation
TEXAS INSTRUMENTS INC28 citations89
US6239003B1May 29, 2001
Method of simultaneous fabrication of isolation and gate regions in a semiconductor device
TEXAS INSTRUMENTS INC12 citations73
US5114530AMay 19, 1992
Interlevel dielectric process
TEXAS INSTRUMENTS INC10 citations73
US4799992AJan 24, 1989
Interlevel dielectric fabrication process
TEXAS INSTRUMENTS INC13 citations73
US4806201AFeb 21, 1989
Use of sidewall oxide to reduce filaments
TEXAS INSTRUMENTS INC18 citations71
US5608256AMar 4, 1997
Recessed sidewall-sealed and sandwiched poly-buffered LOCOS isolation regions, VLSI structures and methods
TEXAS INSTRUMENTS INC3 citations62
US4878996ANov 7, 1989
Method for reduction of filaments between electrodes
TEXAS INSTRUMENTS INC6 citations60