Inventor

BESSER PAUL R

US171 patents

Patents

50 patents

US6465334B1Oct 15, 2002

Enhanced electroless deposition of dielectric precursor materials for use in in-laid gate MOS transistors

ADVANCED MICRO DEVICES INC154 citations99

US7402207B1Jul 22, 2008

Method and apparatus for controlling the thickness of a selective epitaxial growth layer

ADVANCED MICRO DEVICES INC104 citations98

US6811448B1Nov 2, 2004

Pre-cleaning for silicidation in an SMOS process

ADVANCED MICRO DEVICES INC123 citations98

US6787864B2Sep 7, 2004

Mosfets incorporating nickel germanosilicided gate and methods for their formation

ADVANCED MICRO DEVICES INC126 citations98

US6562718B1May 13, 2003

Process for forming fully silicided gates

ADVANCED MICRO DEVICES INC107 citations98

US6475874B2Nov 5, 2002

Damascene NiSi metal gate high-k transistor

ADVANCED MICRO DEVICES INC137 citations98

US6368967B1Apr 9, 2002

Method to control mechanical stress of copper interconnect line using post-plating copper anneal

ADVANCED MICRO DEVICES INC111 citations98

US6300203B1Oct 9, 2001

Electrolytic deposition of dielectric precursor materials for use in in-laid gate MOS transistors

ADVANCED MICRO DEVICES INC101 citations98

US6174743B1Jan 16, 2001

Method of reducing incidence of stress-induced voiding in semiconductor interconnect lines

ADVANCED MICRO DEVICES INC114 citations98

US6518167B1Feb 11, 2003

Method of forming a metal or metal nitride interface layer between silicon nitride and copper

ADVANCED MICRO DEVICES INC81 citations97

US5918149AJun 29, 1999

Reverse electroplating of barrier metal layer to improve electromigration performance in copper interconnect devices

ADVANCED MICRO DEVICES INC62 citations95

US7456062B1Nov 25, 2008

Method of forming a semiconductor device

ADVANCED MICRO DEVICES INC25 citations93

US7001837B2Feb 21, 2006

Semiconductor with tensile strained substrate and method of making the same

ADVANCED MICRO DEVICES INC18 citations93

US6878592B1Apr 12, 2005

Selective epitaxy to improve silicidation

ADVANCED MICRO DEVICES INC51 citations93

US6867428B1Mar 15, 2005

Strained silicon NMOS having silicon source/drain extensions and method for its fabrication

ADVANCED MICRO DEVICES INC46 citations93

US6797614B1Sep 28, 2004

Nickel alloy for SMOS process silicidation

ADVANCED MICRO DEVICES INC24 citations93

US6730576B1May 4, 2004

Method of forming a thick strained silicon layer and semiconductor structures incorporating a thick strained silicon layer

ADVANCED MICRO DEVICES INC28 citations93

US6724087B1Apr 20, 2004

Laminated conductive lines and methods of forming the same

ADVANCED MICRO DEVICES INC19 citations93

US6689689B1Feb 10, 2004

Selective deposition process for allowing damascene-type Cu interconnect lines

ADVANCED MICRO DEVICES INC26 citations93

US6642590B1Nov 4, 2003

Metal gate with PVD amorphous silicon layer and barrier layer for CMOS devices and method of making with a replacement gate process

ADVANCED MICRO DEVICES INC22 citations93

US6614064B1Sep 2, 2003

Transistor having a gate stick comprised of a metal, and a method of making same

ADVANCED MICRO DEVICES INC19 citations93

US6611576B1Aug 26, 2003

Automated control of metal thickness during film deposition

ADVANCED MICRO DEVICES INC19 citations93

US6589866B1Jul 8, 2003

Metal gate with PVD amorphous silicon layer having implanted dopants for CMOS devices and method of making with a replacement gate process

ADVANCED MICRO DEVICES INC25 citations93

US6583012B1Jun 24, 2003

Semiconductor devices utilizing differently composed metal-based in-laid gate electrodes

ADVANCED MICRO DEVICES INC33 citations93

US6528362B1Mar 4, 2003

Metal gate with CVD amorphous silicon layer for CMOS devices and method of making with a replacement gate process

ADVANCED MICRO DEVICES INC27 citations93

US6518154B1Feb 11, 2003

Method of forming semiconductor devices with differently composed metal-based gate electrodes

ADVANCED MICRO DEVICES INC34 citations93

US6511911B1Jan 28, 2003

Metal gate stack with etch stop layer

ADVANCED MICRO DEVICES INC30 citations93

US6455425B1Sep 24, 2002

Selective deposition process for passivating top interface of damascene-type Cu interconnect lines

ADVANCED MICRO DEVICES INC53 citations93

US6444513B1Sep 3, 2002

Metal gate stack with etch stop layer having implanted metal species

ADVANCED MICRO DEVICES INC15 citations93

US6440868B1Aug 27, 2002

Metal gate with CVD amorphous silicon layer and silicide for CMOS devices and method of making with a replacement gate process

ADVANCED MICRO DEVICES INC25 citations93

US6440867B1Aug 27, 2002

Metal gate with PVD amorphous silicon and silicide for CMOS devices and method of making the same with a replacement gate process

ADVANCED MICRO DEVICES INC23 citations93

US6436840B1Aug 20, 2002

Metal gate with CVD amorphous silicon layer and a barrier layer for CMOS devices and method of making with a replacement gate process

ADVANCED MICRO DEVICES INC31 citations93

US6432805B1Aug 13, 2002

Co-deposition of nitrogen and metal for metal silicide formation

ADVANCED MICRO DEVICES INC21 citations93

US6392280B1May 21, 2002

Metal gate with PVD amorphous silicon layer for CMOS devices and method of making with a replacement gate process

ADVANCED MICRO DEVICES INC38 citations93

US6319819B1Nov 20, 2001

Process for passivating top interface of damascene-type Cu interconnect lines

ADVANCED MICRO DEVICES INC49 citations93

US6274511B1Aug 14, 2001

Method of forming junction-leakage free metal silicide in a semiconductor wafer by amorphization of refractory metal layer

ADVANCED MICRO DEVICES INC25 citations93

US6255214B1Jul 3, 2001

Method of forming junction-leakage free metal silicide in a semiconductor wafer by amorphization of source and drain regions

ADVANCED MICRO DEVICES INC38 citations93

US6228761B1May 8, 2001

Method of forming a local interconnect with improved etch selectivity of silicon dioxide/silicide

ADVANCED MICRO DEVICES INC27 citations93

US6165903ADec 26, 2000

Method of forming ultra-shallow junctions in a semiconductor wafer with deposited silicon layer to reduce silicon consumption during salicidation

ADVANCED MICRO DEVICES INC29 citations93

US6150243ANov 21, 2000

Shallow junction formation by out-diffusion from a doped dielectric layer through a salicide layer

ADVANCED MICRO DEVICES INC46 citations93

US5789315AAug 4, 1998

Eliminating metal extrusions by controlling the liner deposition temperature

ADVANCED MICRO DEVICES INC23 citations93

US5582881ADec 10, 1996

Process for deposition of a Ti/TiN cap layer on aluminum metallization and apparatus

ADVANCED MICRO DEVICES INC24 citations93

US7060571B1Jun 13, 2006

Semiconductor device with metal gate and high-k tantalum oxide or tantalum oxynitride gate dielectric

ADVANCED MICRO DEVICES INC35 citations92

Showing the top 50 of 171 patents by PatentIndex Score.

BESSER PAUL R

Patents

Enhanced electroless deposition of dielectric precursor materials for use in in-laid gate MOS transistors

Method and apparatus for controlling the thickness of a selective epitaxial growth layer

Pre-cleaning for silicidation in an SMOS process

Mosfets incorporating nickel germanosilicided gate and methods for their formation

Process for forming fully silicided gates

Damascene NiSi metal gate high-k transistor

Method to control mechanical stress of copper interconnect line using post-plating copper anneal

Electrolytic deposition of dielectric precursor materials for use in in-laid gate MOS transistors

Method of reducing incidence of stress-induced voiding in semiconductor interconnect lines

Method of forming a metal or metal nitride interface layer between silicon nitride and copper

Deposition of a conductor in a via hole or trench

Engineered metal gate electrode

Method of implantation after copper seed deposition

Silicide gate transistors

Process for alloying damascene-type Cu interconnect lines

Wire bonding CU interconnects

Manufacturing capping layer for the fabrication of cobalt salicide structures

Reverse electroplating of barrier metal layer to improve electromigration performance in copper interconnect devices

Method of forming a semiconductor device

Semiconductor with tensile strained substrate and method of making the same

Selective epitaxy to improve silicidation

Strained silicon NMOS having silicon source/drain extensions and method for its fabrication

Nickel alloy for SMOS process silicidation

Method of forming a thick strained silicon layer and semiconductor structures incorporating a thick strained silicon layer

Laminated conductive lines and methods of forming the same

Selective deposition process for allowing damascene-type Cu interconnect lines

Metal gate with PVD amorphous silicon layer and barrier layer for CMOS devices and method of making with a replacement gate process

Transistor having a gate stick comprised of a metal, and a method of making same

Automated control of metal thickness during film deposition

Metal gate with PVD amorphous silicon layer having implanted dopants for CMOS devices and method of making with a replacement gate process

Semiconductor devices utilizing differently composed metal-based in-laid gate electrodes

Metal gate with CVD amorphous silicon layer for CMOS devices and method of making with a replacement gate process

Method of forming semiconductor devices with differently composed metal-based gate electrodes

Metal gate stack with etch stop layer

Selective deposition process for passivating top interface of damascene-type Cu interconnect lines

Metal gate stack with etch stop layer having implanted metal species

Metal gate with CVD amorphous silicon layer and silicide for CMOS devices and method of making with a replacement gate process

Metal gate with PVD amorphous silicon and silicide for CMOS devices and method of making the same with a replacement gate process

Metal gate with CVD amorphous silicon layer and a barrier layer for CMOS devices and method of making with a replacement gate process

Co-deposition of nitrogen and metal for metal silicide formation

Metal gate with PVD amorphous silicon layer for CMOS devices and method of making with a replacement gate process

Process for passivating top interface of damascene-type Cu interconnect lines

Method of forming junction-leakage free metal silicide in a semiconductor wafer by amorphization of refractory metal layer

Method of forming junction-leakage free metal silicide in a semiconductor wafer by amorphization of source and drain regions

Method of forming a local interconnect with improved etch selectivity of silicon dioxide/silicide

Method of forming ultra-shallow junctions in a semiconductor wafer with deposited silicon layer to reduce silicon consumption during salicidation

Shallow junction formation by out-diffusion from a doped dielectric layer through a salicide layer

Eliminating metal extrusions by controlling the liner deposition temperature

Process for deposition of a Ti/TiN cap layer on aluminum metallization and apparatus

Semiconductor device with metal gate and high-k tantalum oxide or tantalum oxynitride gate dielectric