Inventor

NOBLE WENDELL P

US158 patents

⚠️ This page may combine multiple inventors who share the name “NOBLE WENDELL P”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NOBLE WENDELL P

MICRON TECHNOLOGY INC

Memory cell having a vertical transistor with buried source/drain and dual gates

Buried conductors

4 F2 folded bit line DRAM cell structure having buried bit and word lines

Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor

MOSFET technology for programmable address decode and correction

Memory cell having a vertical transistor with buried source/drain and dual gates

Memory cell with vertical transistor and buried word and body lines

Highly conductive composite polysilicon gate for CMOS integrated circuits

Vertical sub-micron CMOS transistors on (110), (111), (311), (511), and higher order surfaces of bulk, SOI and thin film structures and method of forming same

Methods, structures, and circuits for transistors with gate-to-body capacitive coupling

Circuits and methods for dual-gated transistors

Memory cell having a vertical transistor with buried source/drain and dual gates

Methods for dual-gated transistors

Memory cell having a vertical transistor with buried source/drain and dual gates

Discrete devices including EAPROM transistor and NVRAM memory cell with edge defined ferroelectric capacitance, methods for operating same, and apparatuses including same

Structure and method for reducing threshold voltage variations due to dopant fluctuations

Vertical gain cell and array for a dynamic random access memory

Method and apparatus on (110) surfaces of silicon structures with conduction in the &lt;110&gt; direction

Method for forming high density flash memory

Programmable logic array with vertical transistors

Memory cell with vertical transistor and buried word and body lines

Memory cell having a vertical transistor with buried source/drain and dual gates

High density flash memory

Memory address decode array with vertical transistors

Field programmable logic arrays with vertical transistors

Memory cell with vertical transistor and buried word and body lines

Circuits and methods for dual-gated transistors

Circuit and method for a folded bit line memory cell with vertical transistor and trench capacitor

Programmable memory address decode array with vertical transistors

Semiconductor structure having an optical signal path in a substrate and method for forming the same

Trench dram cell with vertical device and buried word lines

Ultra high density flash memory having vertically stacked devices

Ultra high density flash memory

High density flash memory

Method of making memory cell with vertical transistor and buried word and body lines

Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor

Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor

Programmable memory address decode array with vertical transistors

Programmable logic array with vertical transistors

Field programmable logic arrays with vertical transistors

Method for fabricating CMOS transistors having matching characteristics and apparatus formed thereby

DRAM technology compatible non volatile memory cells with capacitors connected to the gates of the transistors

Circuits and methods using vertical complementary transistors

Silicon-on-insulator islands and method for their formation

Dynamic random access memory (DRAM) cells with repressed ferroelectric memory methods of reading same, and apparatuses including same

Method and apparatus on (110) surfaces of silicon structures with conduction in the &lt;110&gt; direction

MICRO TECHNOLOGY INC

Four F2 folded bit line DRAM cell structure having buried bit and word lines

MICRON TECNOLOGY INC

4 F2 folded bit line dram cell structure having buried bit and word lines

MICRON TECHNOLOLGY INC

Method of forming a logic array for a decoder

IBM

On-chip thermometry for control of chip operating temperature

Method and apparatus on (110) surfaces of silicon structures with conduction in the <110> direction

Method and apparatus on (110) surfaces of silicon structures with conduction in the <110> direction