Inventor
POTTER KENNETH H
US20 patents
⚠️ This page may combine multiple inventors who share the name “POTTER KENNETH H”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
CISCO TECH IND
10 patentsUS6757768B1Jun 29, 2004
Apparatus and technique for maintaining order among requests issued over an external bus of an intermediate network node
CISCO TECH IND184 citations98
US6847645B1Jan 25, 2005
Method and apparatus for controlling packet header buffer wrap around in a forwarding engine of an intermediate network node
CISCO TECH IND124 citations97
US6804815B1Oct 12, 2004
Sequence control mechanism for enabling out of order context processing
CISCO TECH IND89 citations97
US6529983B1Mar 4, 2003
Group and virtual locking mechanism for inter processor synchronization
CISCO TECH IND98 citations97
US6662252B1Dec 9, 2003
Group and virtual locking mechanism for inter processor synchronization
CISCO TECH IND46 citations96
US6505269B1Jan 7, 2003
Dynamic addressing mapping to eliminate memory resource contention in a symmetric multiprocessor system
CISCO TECH IND69 citations96
US6895481B1May 17, 2005
System and method for decrementing a reference count in a multicast environment
CISCO TECH IND23 citations92
US6757298B1Jun 29, 2004
VLAN trunking over ATM PVCs (VTAP)
CISCO TECH IND41 citations92
US6708258B1Mar 16, 2004
Computer system for eliminating memory read-modify-write operations during packet transfers
CISCO TECH IND25 citations92
US6976149B1Dec 13, 2005
Mapping technique for computing addresses in a memory of an intermediate network node
CISCO TECH IND34 citations91
CISCO TECH INC
10 patentsUS6832279B1Dec 14, 2004
Apparatus and technique for maintaining order among requests directed to a same address on an external bus of an intermediate network node
CISCO TECH INC94 citations97
US7623455B2Nov 24, 2009
Method and apparatus for dynamic load balancing over a network link bundle
CISCO TECH INC103 citations94
US7155722B1Dec 26, 2006
System and method for process load balancing in a multi-processor environment
CISCO TECH INC57 citations94
US7254687B1Aug 7, 2007
Memory controller that tracks queue operations to detect race conditions
CISCO TECH INC33 citations92
US7245615B1Jul 17, 2007
Multi-link protocol reassembly assist in a parallel 1-D systolic array system
CISCO TECH INC20 citations91
US7174394B1Feb 6, 2007
Multi processor enqueue packet circuit
CISCO TECH INC29 citations91
US7124231B1Oct 17, 2006
Split transaction reordering circuit
CISCO TECH INC40 citations91
US7290105B1Oct 30, 2007
Zero overhead resource locks with attributes
CISCO TECH INC47 citations90
US7447872B2Nov 4, 2008
Inter-chip processor control plane communication
CISCO TECH INC17 citations82
US7286532B1Oct 23, 2007
High performance interface logic architecture of an intermediate network node
CISCO TECH INC15 citations80