Inventor · disambiguated record
Cang Ngoc Tran
Also filed as: TRAN CANG · TRAN CANG N · TRAN CANG NGOC
11 granted patents·531 citations·filing 1992–1998
92Inventor score
Technology areasG06F
Files withIBM11
Top patents by PatentIndex Score
11 records- 0185US5901294AMethod and system for bus arbitration in a multiprocessor system utilizing simultaneous variable-width bus accessIBM·Filed 1997·Granted May 4, 1999·126 cites·6 claims
- 0281US5913044AMethod and system for simultaneous variable-width bus access in a multiprocessor systemIBM·Filed 1997·Granted Jun 15, 1999·97 cites·12 claims
- 0377US5893921AMethod for maintaining memory coherency in a computer system having a cache utilizing snoop address injection during a read transaction by a dual memory bus controllerIBM·Filed 1995·Granted Apr 13, 1999·91 cites·8 claims
- 0476US5255374ABus interface logic for computer system having dual bus architectureIBM·Filed 1992·Granted Oct 19, 1993·74 cites·14 claims
- 0572US5930484AMethod and system for input/output control in a multiprocessor system utilizing simultaneous variable-width bus accessIBM·Filed 1997·Granted Jul 27, 1999·62 cites·11 claims
- 0657US5761533AComputer system with varied data transfer speeds between system components and memoryIBM·Filed 1994·Granted Jun 2, 1998·33 cites·7 claims
- 0742US6178497B1System and method for determining the relative age of instructions in a processorIBM·Filed 1998·Granted Jan 23, 2001·14 cites·13 claims
- 0840US5687350AProtocol and system for performing line-fill address during copy-back operationIBM·Filed 1995·Granted Nov 11, 1997·15 cites·10 claims
- 0939US5926628ASelectable priority bus arbitration schemeIBM·Filed 1997·Granted Jul 20, 1999·11 cites·25 claims
- 1034US5771372AApparatus for delaying the output of data onto a system busIBM·Filed 1995·Granted Jun 23, 1998·8 cites·14 claims
- 1129US5784580ASystem and method for communicating between devicesIBM·Filed 1996·Granted Jul 21, 1998·0 cites·27 claims
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