Inventor
MARIETTA BRYAN D
US21 patents
⚠️ This page may combine multiple inventors who share the name “MARIETTA BRYAN D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
MARIETTA BRYAN D
6 patentsUS8560782B2Oct 15, 2013
Method and apparatus for determining access permissions in a partitioned data processing system
MARIETTA BRYAN D5 citations69
US9442870B2Sep 13, 2016
Interrupt priority management using partition-based priority blocking processor registers
MARIETTA BRYAN D2 citations60
US9436626B2Sep 6, 2016
Processor interrupt interface with interrupt partitioning and virtualization enhancements
MARIETTA BRYAN D2 citations60
US9229884B2Jan 5, 2016
Virtualized instruction extensions for system partitioning
MARIETTA BRYAN D2 citations60
US9104472B2Aug 11, 2015
Write transaction interpretation for interrupt assertion
MARIETTA BRYAN D0 citations51
US9152587B2Oct 6, 2015
Virtualized interrupt delay mechanism
MARIETTA BRYAN D0 citations50
FREESCALE SEMICONDUCTOR INC
5 patentsUS7106742B1Sep 12, 2006
Method and system for link fabric error detection and message flow control
FREESCALE SEMICONDUCTOR INC46 citations91
US6862283B2Mar 1, 2005
Method and apparatus for maintaining packet ordering with error recovery among multiple outstanding packets between two devices
FREESCALE SEMICONDUCTOR INC22 citations91
US7849247B2Dec 7, 2010
Interrupt controller for accelerated interrupt handling in a data processing system and method thereof
FREESCALE SEMICONDUCTOR INC11 citations84
US6754752B2Jun 22, 2004
Multiple memory coherence groups in a single system and method therefor
FREESCALE SEMICONDUCTOR INC7 citations73
US9900390B2Feb 20, 2018
Method and apparatus for controlling wake events in a data processing system
FREESCALE SEMICONDUCTOR INC2 citations70
MOTOROLA INC
3 patentsUS6150724ANov 21, 2000
Multi-chip semiconductor device and method for making the device by using multiple flip chip interfaces
MOTOROLA INC338 citations96
US5848025ADec 8, 1998
Method and apparatus for controlling a memory device in a page mode
MOTOROLA INC60 citations93
US6678773B2Jan 13, 2004
Bus protocol independent method and structure for managing transaction priority, ordering and deadlocks in a multi-processing system
MOTOROLA INC41 citations91
HEWLETT PACKARD CO
2 patentsCONVEX COMPUTER CORP
2 patentsSAMSUNG ELECTRONICS CO LTD
2 patentsUS11467902B2Oct 11, 2022
Apparatus to insert error-correcting coding (ECC) information as data within dynamic random access memory (DRAM)
SAMSUNG ELECTRONICS CO LTD0 citations62
US10853168B2Dec 1, 2020
Apparatus to insert error-correcting coding (ECC) information as data within dynamic random access memory (DRAM)
SAMSUNG ELECTRONICS CO LTD1 citations62