Inventor

RAVI SRIVATHS

IN13 patents

⚠️ This page may combine multiple inventors who share the name “RAVI SRIVATHS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TEXAS INSTRUMENTS INC

3 patents

US8671329B2Mar 11, 2014

Low overhead and timing improved architecture for performing error checking and correction for memories and buses in system-on-chips, and other circuits, systems and processes

TEXAS INSTRUMENTS INC17 citations92

US11333707B2May 17, 2022

Testing of integrated circuits during at-speed mode of operation

TEXAS INSTRUMENTS INC3 citations67

US8839063B2Sep 16, 2014

Circuits and methods for dynamic allocation of scan test resources

TEXAS INSTRUMENTS INC2 citations60

NEC LAB AMERICA INC

3 patents

US7278123B2Oct 2, 2007

System-level test architecture for delivery of compressed tests

NEC LAB AMERICA INC40 citations90

US7529669B2May 5, 2009

Voice-based multimodal speaker authentication using adaptive training and applications thereof

NEC LAB AMERICA INC13 citations84

US7260809B2Aug 21, 2007

Power estimation employing cycle-accurate functional descriptions

NEC LAB AMERICA INC4 citations62

NEC USA INC

1 patent

US7134100B2Nov 7, 2006

Method and apparatus for efficient register-transfer level (RTL) power estimation

NEC USA INC59 citations96

KUMAR SANJAY

1 patent

US8438344B2May 7, 2013

Low overhead and timing improved architecture for performing error checking and correction for memories and buses in system-on-chips, and other circuits, systems and processes

KUMAR SANJAY19 citations91

HALES ALAN DAVID

1 patent

US8205125B2Jun 19, 2012

Enhanced control in scan tests of integrated circuits with partitioned scan chains

HALES ALAN DAVID40 citations86

NEC CORP

1 patent

US7173906B2Feb 6, 2007

Flexible crossbar switching fabric

NEC CORP10 citations79

GANGASANI SWATHI

1 patent

US8286042B2Oct 9, 2012

On-chip seed generation using boolean functions for LFSR re-seeding based logic BIST techniques for low cost field testability

GANGASANI SWATHI17 citations77

RAVI SRIVATHS

1 patent

US8856601B2Oct 7, 2014

Scan compression architecture with bypassable scan chains for low test mode power

RAVI SRIVATHS3 citations54

SHAH MALAV SHRIKANT

1 patent

US8527821B2Sep 3, 2013

Hybrid test compression architecture using multiple codecs for low pin count and high compression devices

SHAH MALAV SHRIKANT0 citations27