Inventor

HOYT BRADLEY D

US11 patents

Patents

11 patents

US5604877AFeb 18, 1997

Method and apparatus for resolving return from subroutine instructions in a computer processor

INTEL CORP209 citations98

US5574871ANov 12, 1996

Method and apparatus for implementing a set-associative branch target buffer

INTEL CORP122 citations98

US5812839ASep 22, 1998

Dual prediction branch system having two step of branch recovery process which activated only when mispredicted branch is the oldest instruction in the out-of-order unit

INTEL CORP118 citations97

US5903751AMay 11, 1999

Method and apparatus for implementing a branch target buffer in CISC processor

INTEL CORP38 citations96

US5768576AJun 16, 1998

Method and apparatus for predicting and handling resolving return from subroutine instructions in a computer processor

INTEL CORP75 citations96

US5584001ADec 10, 1996

Branch target buffer for dynamically predicting branch instruction outcomes using a predicted branch history

INTEL CORP95 citations96

US5577217ANov 19, 1996

Method and apparatus for a branch target buffer with shared branch pattern tables for associated branch predictions

INTEL CORP60 citations95

US5918046AJun 29, 1999

Method and apparatus for a branch instruction pointer table

INTEL CORP30 citations92

US5944817AAug 31, 1999

Method and apparatus for implementing a set-associative branch target buffer

INTEL CORP27 citations91

US5706492AJan 6, 1998

Method and apparatus for implementing a set-associative branch target buffer

INTEL CORP22 citations91

US5668985ASep 16, 1997

Decoder having a split queue system for processing intstructions in a first queue separate from their associated data processed in a second queue

INTEL CORP13 citations73